EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 359

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 11: Configuring Stratix III Devices
Passive Serial Configuration
Passive Serial Configuration
PS Configuration Using a MAX II Device as an External Host
© March 2011 Altera Corporation
f
1
For more information about programming serial configuration devices and fast AS
Configuration Timing, refer to the
EPCS16, EPCS64, and EPCS128) Data Sheet
You can program PS configuration of Stratix III devices using an intelligent host, such
as a MAX II device or microprocessor with flash memory, or a download cable. In the
PS scheme, an external host (a MAX II device, embedded processor, or host PC)
controls configuration. Configuration data is clocked into the target Stratix III device
by using the DATA0 pin at each rising edge of DCLK.
The Stratix III decompression and design security features are fully available when
configuring your Stratix III device using PS mode.
Table 11–9
Table 11–9. Stratix III MSEL Pin Settings for PS Configuration Scheme
In this configuration scheme, you can use a MAX II device as an intelligent host that
controls the transfer of configuration data from a storage device, such as flash
memory, to the target Stratix III device. You can store configuration data in .rbf, .hex,
or .ttf format.
Stratix III device and a MAX II device for single device configuration.
Figure 11–13. Single Device PS Configuration Using an External Host
Note to
(1) Connect the resistor to a supply that provides an acceptable input signal for the Stratix III device. V
PS
high enough to meet the V
configuration systems’ I/O with V
Figure
(MAX II Device or
Microprocessor)
lists the MSEL pin settings when using the PS configuration scheme.
11–13:
External Host
ADDR
Figure 11–13
Memory
Configuration Scheme
DATA0
IH
specification of the I/O on the external host. It is recommended to power up all
shows the configuration interface connections between a
CCPGM
.
10 k
V CCPGM (1)
Serial Configuration Devices (EPCS1, EPCS4,
Ω
10 k
Ω
V CCPGM (1)
in the Configuration Handbook.
GND
CONF_DONE
nSTATUS
nCE
DATA0
nCONFIG
DCLK
Stratix III Device
MSEL2
Stratix III Device Handbook, Volume 1
0
MSEL2
MSEL1
MSEL0
nCEO
MSEL1
N.C.
1
GND
V
CCPGM
CCPGM
MSEL0
must be
0
11–27