EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 361

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 11: Configuring Stratix III Devices
Passive Serial Configuration
© March 2011 Altera Corporation
1
1
An optional INIT_DONE pin is available, which signals the end of initialization and
the start of user-mode with a low-to-high transition. The Enable INIT_DONE Output
option is available in the Quartus II software on the General tab of the Device and
Pin Options dialog box. If you use the INIT_DONE pin, it will be high due to an
external 10-kΩ pull-up resistor when nCONFIG is low and during the beginning of
configuration. When the option bit to enable INIT_DONE is programmed into the
device (during the first frame of configuration data), the INIT_DONE pin will go low.
When initialization is complete, the INIT_DONE pin will be released and pulled high.
The MAX II device must be able to detect this low-to-high transition, which signals
the device has entered user mode. When initialization is complete, the device enters
user mode. In user mode, the user I/O pins will no longer have weak pull-up resistors
and will function as assigned in your design.
To ensure DCLK and DATA0 are not left floating at the end of configuration, the
MAX II device must drive them either high or low, whichever is convenient on your
board. The DATA[0] pin is available as a user I/O pin after configuration. When you
choose the PS scheme as a default in the Quartus II software, this I/O pin is tri-stated
in user mode and should be driven by the MAX II device. To change this default
option in the Quartus II software, click the Dual-Purpose Pins tab of the Device and
Pin Options dialog box.
The configuration clock (DCLK) speed must be below the specified frequency to
ensure correct configuration. No maximum DCLK period exists, which means you can
pause configuration by halting DCLK for an indefinite amount of time.
If an error occurs during configuration, the device drives its nSTATUS pin low,
resetting itself internally. The low signal on the nSTATUS pin also alerts the MAX II
device that there is an error. If the Auto-restart configuration after error option
(available in the Quartus II software on the General tab of the Device and Pin
Options dialog box) is turned on, the Stratix III device releases nSTATUS after a reset
time-out period (maximum of 100 μs). After nSTATUS is released and pulled high by a
pull-up resistor, the MAX II device can attempt to reconfigure the target device
without needing to pulse nCONFIG low. If this option is turned off, the MAX II device
must generate a low-to-high transition (with a low pulse of at least 2 μs) on nCONFIG
to restart the configuration process.
If you have enabled the Auto-restart configuration after error option, the nSTATUS pin
transitions from high to low and back again to high when a configuration error is
detected. This appears as a low pulse at the nSTATUS pin with a minimum pulse width
of 10 μs to a maximum pulse width of 500 μs, as defined in the t
The MAX II device can also monitor the CONF_DONE and INIT_DONE pins to ensure
successful configuration. The CONF_DONE pin must be monitored by the MAX II
device to detect errors and determine when programming completes. If all
configuration data is sent, but CONF_DONE or INIT_DONE have not gone high, the
MAX II device must reconfigure the target device.
If you use the optional CLKUSR pin and nCONFIG is pulled low to restart
configuration during device initialization, you must ensure that CLKUSR continues
toggling during the time nSTATUS is low (maximum of 100 µs).
Stratix III Device Handbook, Volume 1
STATUS
specification.
11–29