EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 366

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

11–34
Stratix III Device Handbook, Volume 1
1
Upon power-up, the Stratix III devices go through a POR. The POR delay is
dependent on the PORSEL pin setting. When PORSEL is driven low, the POR time is
approximately 100 ms. If PORSEL is driven high, the POR time is approximately
12 ms. During POR, the device will reset, hold nSTATUS low, and tri-state all user I/O
pins. After the device successfully exits POR, all user I/O pins continue to be
tri-stated. If nIO_pullup is driven low during power-up and configuration, the user
I/O pins and dual-purpose I/O pins will have weak pull-up resistors which are on
(after POR) before and during configuration. If nIO_pullup is driven high, the weak
pull-up resistors are disabled.
The configuration cycle consists of three stages: reset, configuration and initialization.
While nCONFIG or nSTATUS are low, the device is in reset. To initiate configuration in
this scheme, the download cable generates a low-to-high transition on the nCONFIG
pin.
To begin configuration, power the V
where the configuration and JTAG pins reside) to the appropriate voltage levels.
When nCONFIG goes high, the device comes out of reset and releases the open-drain
nSTATUS pin, which is then pulled high by an external 10-kΩ pull-up resistor. After
nSTATUS is released, the device is ready to receive configuration data and the
configuration stage begins. The programming hardware or download cable then
places the configuration data one bit at a time on the device's DATA0 pin. The
configuration data is clocked into the target device until CONF_DONE goes high. The
CONF_DONE pin must have an external 10-kΩ pull-up resistor in order for the device
to initialize.
When using a download cable, setting the Auto-restart configuration after error
option does not affect the configuration cycle because you must manually restart
configuration in the Quartus II software when an error occurs. Additionally, the
Enable user-supplied start-up clock (CLKUSR) option has no affect on the device
initialization since this option is disabled in the SOF when programming the device
using the Quartus II programmer and download cable. Therefore, if you turn on the
CLKUSR option, you do not need to provide a clock on CLKUSR when you are
configuring the device with the Quartus II programmer and a download cable.
Figure 11–17
MasterBlaster, ByteBlaster II, ByteBlasterMV, or EthernetBlaster cable.
shows PS configuration for Stratix III devices using a USB-Blaster,
CC
, V
CCIO
, V
CCPGM
, and V
Chapter 11: Configuring Stratix III Devices
CCPD
© March 2011 Altera Corporation
voltages (for the banks
Passive Serial Configuration