EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 367

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 11: Configuring Stratix III Devices
Passive Serial Configuration
Figure 11–17. PS Configuration Using a Download Cable
Notes to
(1) You should connect the pull-up resistor to the same supply voltage (V
(2) You only need the pull-up resistors on DATA0 and DCLK if the download cable is the only configuration scheme used on your board. This ensures
(3) Pin 6 of the header is a V
© March 2011 Altera Corporation
ByteBlasterMV, or EthernetBlaster cable.
that DATA0 and DCLK are not left floating after configuration. For example, if you are also using a configuration device, you do not need the
pull-up resistors on DATA0 and DCLK.
Serial/USB Communications Cable Data Sheet
is a no connect.
Figure
11–17:
V CCPGM (1)
10 kΩ
10 kΩ
(2)
V CCPGM (1)
(2)
You can use a download cable to configure multiple Stratix III devices by connecting
each device's nCEO pin to the subsequent device's nCE pin. The first device's nCE pin
is connected to GND while its nCEO pin is connected to the nCE of the next device in
the chain. The last device's nCE input comes from the previous device, while its nCEO
pin is left floating. All other configuration pins (nCONFIG, nSTATUS, DCLK, DATA0,
and CONF_DONE) are connected to every device in the chain. Because all CONF_DONE
pins are tied together, all devices in the chain initialize and enter user mode at the
same time.
In addition, because the nSTATUS pins are tied together, the entire chain halts
configuration if any device detects an error. The Auto-restart configuration after
error option does not affect the configuration cycle because you must manually restart
configuration in the Quartus II software when an error occurs.
V CCPGM (1)
IO
reference voltage for the MasterBlaster output driver. V
10 kΩ
V CCPGM
GND
GND
for this value. In the USB-Blaster, ByteBlaster II, ByteBlasterMV, or EthernetBlaster cable, this pin
MSEL2
MSEL1
MSEL0
nCE
DCLK
DATA0
nCONFIG
Stratix III Device
CONF_DONE
nSTATUS
CC PGM
nCEO
) as the USB-Blaster, MasterBlaster (V
N.C.
V CCPGM (1)
IO
should match the device's V
10 kΩ
V CCPGM (1)
10 kΩ
Pin 1
10-Pin Male Header
Download Cable
Stratix III Device Handbook, Volume 1
(PS Mode)
Shield
GND
C CP GM
V CCPGM
IO
V
pin), ByteBlaster II,
IO
. Refer to the
(3)
GND
MasterBlaster
11–35