EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 371
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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Chapter 11: Configuring Stratix III Devices
JTAG Configuration
Figure 11–19. JTAG Configuration of a Single Device Using a Download Cable
Notes to
(1) You should connect the pull-up resistor to the same supply voltage as the USB-Blaster, MasterBlaster (VIO pin), ByteBlaster II, ByteBlasterMV,
(2) You should connect the nCONFIG and MSEL[2..0] pins to support a non-JTAG configuration scheme. If you only use the JTAG configuration,
(3) Pin 6 of the header is a V
(4) You must connect nCE to GND or drive it low for successful JTAG configuration.
(5) Pull-up resistor values can vary from 1 kΩ to 10 kΩ.
© March 2011 Altera Corporation
or EthernetBlaster cables. The voltage supply can be connected to the V
connect nCONFIG to V
Serial/USB Communications Cable Data Sheet
no connect.
Figure
11–19:
V CCPGM (1)
Figure 11–19
To configure a single device in a JTAG chain, the programming software places all
other devices in bypass mode. In bypass mode, devices pass programming data from
the TDI pin to the TDO pin through a single bypass register without being affected
internally. This scheme enables the programming software to program or verify the
target device. Configuration data driven into the device appears on the TDO pin one
clock cycle later.
The Quartus II software verifies successful JTAG configuration upon completion. At
the end of configuration, the software checks the state of CONF_DONE through the
JTAG port. When Quartus II generates a JAM file (.jam) for a multi-device chain, it
contains instructions so that all the devices in the chain will be initialized at the same
time. If CONF_DONE is not high, the Quartus II software indicates that configuration
has failed. If CONF_DONE is high, the software indicates that configuration was
successful. After the configuration bitstream is transmitted serially through the JTAG
TDI port, the TCK port is clocked an additional 1,094 cycles to perform device
initialization.
CC PGM
IO
reference voltage for the MasterBlaster output driver. V
10 kΩ
, and MSEL[2..0] to ground. Pull DCLK either high or low, whichever is convenient on your board.
V CCPGM (1)
GND
10 kΩ
(2)
(2)
(2)
N.C.
shows JTAG configuration of a single Stratix III device.
for this value. In the USB-Blaster, ByteBlaster II, ByteBlasterMV, and EthernetBlaster, this pin is a
nCE0
nCE
nSTATUS
CONF_DONE
nCONFIG
MSEL[2..0]
DCLK
Stratix III Device
(4)
TRST
TDO
TMS
TCK
TDI
V CCPD
(5)
CCPD
V CCPD (1)
V CCPD (1)
of the device.
(5)
IO
should match the device's V
1 kΩ
GND
Pin 1
10-Pin Male Header
Download Cable
(JTAG Mode)
(Top View)
GND
V CCPD
Stratix III Device Handbook, Volume 1
V
IO
(3)
C CPD
GND
. Refer to the
MasterBlaster
11–39
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