EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 377

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 11: Configuring Stratix III Devices
Device Configuration Pins
Table 11–14. Dedicated Configuration Pins on the Stratix III Device (Part 2 of 5)
© March 2011 Altera Corporation
nIO_PULLUP
MSEL[2..0]
nCONFIG
Pin Name
User Mode
N/A
N/A
N/A
Configuration
Scheme
All
All
All
Pin Type
Input
Input
Input
Dedicated input that chooses whether the internal
pull-up resistor on the user I/O pins and dual-purpose
I/O pins (nCSO, nASDO, DATA[7..0], nWS, nRS,
RDYnBSY, nCS, CLKUSR, INIT_DONE) are on or off
before and during configuration. A logic high (1.8 V, 2.5
V, 3.0 V, 3.3 V) turns off the weak internal pull-up
resistors, while a logic low turns them on.
The nIO-PULLUP input buffer is powered by VCCPGM
and has an internal 5-kΩ pull-down resistor that is
always active. You can tie the nIO-PULLUP directly to
VCCPGM or use a 1-kΩ pull-up resistor or tie it directly
to GND.
3-bit configuration input that sets the Stratix III device
configuration scheme. Refer to
appropriate connections.
You must hard-wire these pins to VCCPGM or GND.
The MSEL[2..0] pins have internal 5-kΩ pull-down
resistors that are always active.
Configuration control input. Pulling this pin low during
user-mode will cause the device to lose its configuration
data, enter a reset state, and tri-state all I/O pins.
Returning this pin to a logic high level will initiate a
reconfiguration.
Configuration is possible only if this pin is high, except
in JTAG programming mode when nCONFIG is
ignored.
Description
Stratix III Device Handbook, Volume 1
Table 11–1
for the
11–45