EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 379

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 11: Configuring Stratix III Devices
Device Configuration Pins
Table 11–14. Dedicated Configuration Pins on the Stratix III Device (Part 4 of 5)
© March 2011 Altera Corporation
CONF_DONE
nCE
nCEO
ASDO
nCSO
Pin Name
(1)
(1)
User Mode
N/A
N/A
N/A
N/A
N/A
Configuration
Scheme
AS
AS
All
All
All
Bi-directional
open-drain
Pin Type
Output
Output
Output
Input
Status output. The target device drives the CONF_DONE
pin low before and during configuration. After all
configuration data is received without error and the
initialization cycle starts, the target device releases
CONF_DONE.
Status input. After all data is received and CONF_DONE
goes high, the target device initializes and enters user
mode. The CONF_DONE pin must have an external
10-kΩ pull-up resistor in order for the device to
initialize.
Driving CONF_DONE low after configuration and
initialization does not affect the configured device. Do
not connect bus holds or ADC to CONF_DONE pin.
Active-low chip enable. The nCE pin activates the device
with a low signal to allow configuration. The nCE pin
must be held low during configuration, initialization, and
user mode. In single device configuration, it should be
tied low. In multi-device configuration, nCE of the first
device is tied low while its nCEO pin is connected to
nCE of the next device in the chain.
The nCE pin must also be held low for successful JTAG
programming of the device.
Output that drives low when device configuration is
complete. In single device configuration, this pin is left
floating. In multi-device configuration, this pin feeds the
next device's nCE pin. The nCEO of the last device in
the chain is left floating.
The nCEO pin is powered by V
Control signal from the Stratix III device to the serial
configuration device in AS mode used to read out
configuration data.
In AS mode, ASDO has an internal pull-up resistor that
is always active.
Output control signal from the Stratix III device to the
serial configuration device in AS mode that enables the
configuration device.
In AS mode, nCSO has an internal pull-up resistor that
is always active.
Description
Stratix III Device Handbook, Volume 1
CC PGM
.
11–47