EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 380

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

11–48
Table 11–14. Dedicated Configuration Pins on the Stratix III Device (Part 5 of 5)
Stratix III Device Handbook, Volume 1
DCLK
DATA0
DATA[7..1]
Note to
(1) To tri-state AS configuration pins in AS configuration scheme, turn on Enable input tri-state on active configuration pins in user mode option
Pin Name
from the Device and Pin Options dialog box. This tri-states DCLK, nCSO, Data0, and ASDO pins. Dual-purpose Pins Setting for Data0 is
ignored. To set Data0 to a different setting, for example to use Data0 pin as a regular I/O in user mode, turn off Enable input tri-state on
active configuration pins in user mode option and set your desired setting from the Dual-purpose Pins Setting menu.
(1)
Table
(1)
11–14:
mode. I/O in
User Mode
PS or FPP
N/A in AS
mode
N/A
I/O
schemes (FPP)
Configuration
schemes (PS,
Synchronous
configuration
configuration
PS, FPP, AS
FPP, AS)
Scheme
Parallel
Output (AS)
Input (PS,
Pin Type
Inputs
Input
FPP)
DCLK has an internal pull-up resistor (typically 25 kΩ)
that is always active.
In AS mode, DCLK is an output from the Stratix III
device that provides timing for the configuration
interface. After AS configuration, this pin is driven to an
inactive state. In schemes that use a configuration
device, DCLK will be driven low after configuration is
done. In schemes that use a control host, DCLK should
be driven either high or low, whichever is more
convenient. Toggling this pin after configuration does
not affect the configured device.
Data input. In serial configuration modes, bit-wide
configuration data is presented to the target device on
the DATA0 pin.
In AS mode, DATA0 has an internal pull-up resistor that
is always active.
After PS or FPP configuration, DATA0 is available as a
user I/O pin and the state of this pin depends on the
Dual-Purpose Pin settings.
Data inputs. Byte-wide configuration data is presented
to the target device on DATA[7..0].
In serial configuration schemes, they function as user
I/O pins during configuration, which means they are
tri-stated.
After configuration, DATA[7..1] are available as user
I/O pins and the state of these pin depends on the
Dual-Purpose Pin settings.
Chapter 11: Configuring Stratix III Devices
Description
© March 2011 Altera Corporation
Device Configuration Pins