EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 392

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

12–8
Figure 12–5. Remote System Upgrade Circuit Data Path
Note to
(1) RU_DOUT, RU_SHIFTnLD, RU_CAPTnUPDT, RU_CLK, RU_DIN, RU_nCONFIG, and RU_nRSTIMER signals are internally controlled by
Remote System Upgrade Registers
Table 12–2. Remote System Upgrade Registers (Part 1 of 2)
Stratix III Device Handbook, Volume 1
Shift register
Control register
the ALTREMOTE_UPDATE megafunction. For more information about the ALTREMOTE_UPDATE megafunction, refer to the
ALTREMOTE_MUPDATE Megafunction User
Register
Figure
RU_DOUT
12–4:
dout
Accessible by the logic array and allows the update, status, and control registers to be written and
sampled by user logic. Write access is enabled in remote update mode for factory configurations to allow
writes to the update register.
Contains the current page address, the user watchdog timer settings, and one bit specifying whether the
current configuration is a factory configuration or an application configuration. During a read operation of
an application configuration, this register is read into the shift register. When a reconfiguration cycle is
initiated, the contents of the update register are written into the control register.
Status Register (SR)
The remote system upgrade block contains a series of registers that store the page
addresses, watchdog timer settings, and status information. These registers are
detailed in
Bit [4..0]
[4..0]
RU_SHIFTnLD
capture
Shift Register
din
Table
Guide.
RU_CAPTnUPDT
dout
12–2.
Control Register
Update Register
Logic Array
Bit [37..0]
[37..0]
[37..0]
Logic Array
clkout
(Note 1)
Logic Array
capture
capture
update
RU_CLK
Description
clkin
din
update
Chapter 12: Remote System Upgrades with Stratix III Devices
RU_DIN RU_nCONFIG
Internal Oscillator
Machine
State
RSU
Dedicated Remote System Upgrade Circuitry
timeout
© March 2010 Altera Corporation
RU_nRSTIMER
Watchdog
Timer
User