EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 393

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 12: Remote System Upgrades with Stratix III Devices
Dedicated Remote System Upgrade Circuitry
© March 2010
Table 12–2. Remote System Upgrade Registers (Part 2 of 2)
Table 12–3. Remote System Upgrade Control Register Contents (Part 1 of 2)
Update register
Status register
AnF
PGM[23..0]
Control Register Bit
Register
(1)
Altera Corporation
Contains data similar to that in the control register. However, it can only be updated by the factory
configuration by shifting data into the shift register and issuing an update operation. When a
reconfiguration cycle is triggered by the factory configuration, the control register is updated with the
contents of the update register. During a capture in a factory configuration, this register is read into the
shift register.
Written to by the remote system upgrade circuitry on every reconfiguration to record the cause of the
reconfiguration. This information is used by the factory configuration to determine the appropriate action
following a reconfiguration. During a capture cycle, this register is read into the shift register.
The remote system upgrade control and status registers are clocked by the 10-MHz
internal oscillator (the same oscillator that controls the user watchdog timer).
However, the remote system upgrade shift and update registers are clocked by the
user clock input (RU_CLK).
Remote System Upgrade Control Register
The remote system upgrade control register stores the application configuration page
address and user watchdog timer settings. The control register functionality depends
on the remote system upgrade mode selection. In remote update mode, the control
register page address bits are set to all zeros (24'b0 = 0×000000) at power up in
order to load the factory configuration. A factory configuration in remote update
mode has write access to this register.
The control register bit positions are shown in
In the figure, the numbers show the bit position of a setting within a register. For
example, bit number 8 is the enable bit for the watchdog timer.
Figure 12–6. Remote System Upgrade Control Register
The application-not-factory (AnF) bit indicates whether the current configuration
loaded in the Stratix III device is the factory configuration or an application
configuration. This bit is set low by the remote system upgrade circuitry when an
error condition causes a fall-back to the factory configuration. When the AnF bit is
high, the control register access is limited to read operations. When the AnF bit is low,
the register allows write operations and disables the watchdog timer.
In remote update mode, factory configuration design sets this bit high (1'b1) when
updating the contents of the update register with the application page address and
watchdog timer settings.
Remote update
Remote update
Remote System
Upgrade Mode
37 36 35 34 33 32 31 30 29 28 27 26
Wd_timer[11..0]
1'b0
24'b0×000000
Value
(2)
Description
Application not factory
AS configuration start address
(StAdd[23..0])
Wd_en
Figure 12–6
25
24 23 22 .. 3
Stratix III Device Handbook, Volume 1
PGM[23..0]
and defined in
Definition
2
1
AnF
0
Table
12–3.
12–9