EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 404

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

13–6
Table 13–3. Stratix III Device Boundary Scan Cell Descriptions
Stratix III Device Handbook, Volume 1
User I/O pins
Dedicated clock
input
Dedicated input
(2)
Dedicated
bi-directional
(open drain)
Dedicated
bi-directional
Dedicated output
(5)
Notes to
(1) TDI, TDO, TMS, TCK, TRST, all V
(2) This includes pins PLL_ENA, nCONFIG, MSEL0, MSEL1, MSEL2, nCE, PORSEL, and nIO_PULLUP.
(3) This includes pins CONF_DONE and nSTATUS.
(4) This includes pin DCLK.
(5) This includes pin nCEO.
Pin Type
Table
(3)
(4)
13–3:
Table 13–3
within Stratix III devices.
Register
Capture
Output
OUTJ
OUTJ
OUTJ
0
0
0
CC
and GND pin types, VREF, and TEMP_DIODE pins do not have BSCs.
Captures
lists the capture and update register capabilities of all boundary-scan cells
Register
Capture
OEJ
OEJ
OEJ
OE
1
1
0
PIN_IN
PIN_IN
PIN_IN
PIN_IN
PIN_IN
Register
Capture
Input
0
Chapter 13: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices
PIN_OUT
Register
Update
(Note 1)
Output
—
—
—
—
—
OE Update
Register
PIN_OE
Drives
—
—
—
—
—
IEEE Std. 1149.1 Boundary-Scan Register
Register
Update
Input
INJ
—
—
—
—
—
© July 2010 Altera Corporation
PIN_IN drives to
clock network or
logic array
PIN_IN drives to
control logic
PIN_IN drives to
configuration
control
PIN_IN drives to
configuration
control and OUTJ
drives to output
buffer
OUTJ drives to
output buffer
Comments
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