EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 408

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

13–10
Stratix III Device Handbook, Volume 1
During the SHIFT_IR state, an instruction code is entered by shifting data on the TDI
pin on the rising edge of TCK. The last bit of the instruction code is clocked at the same
time that the next state, EXIT1_IR, is activated. Set TMS high to activate the
EXIT1_IR state. After the EXIT1_IR state is activated, TDO becomes tri-stated again.
TDO is always tri-stated except in the SHIFT_IR and SHIFT_DR states. After an
instruction code is entered correctly, the TAP controller advances to serially shift test
data in one of three modes.
The three serially shift test data instruction modes are discussed in the following
sections:
■
■
■
“SAMPLE/PRELOAD Instruction Mode” on page 13–11
“EXTEST Instruction Mode” on page 13–13
“BYPASS Instruction Mode” on page 13–15
Chapter 13: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices
IEEE Std. 1149.1 BST Operation Control
© July 2010 Altera Corporation