EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 413

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 13: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices
IEEE Std. 1149.1 BST Operation Control
BYPASS Instruction Mode
Figure 13–12. BYPASS Shift Data Register Waveforms
Note to
(1) Data shifted into TDI on the rising edge of TCK is shifted out of TDO on the falling edge of the same TCK pulse.
© July 2010
Figure
TAP_STATE
TMS
TDO
TCK
TDI
Altera Corporation
13–12:
SHIFT_IR
Instruction Code
The BYPASS mode is activated when an instruction code of all ones is loaded in the
instruction register. This mode allows the boundary scan data to pass the selected
device synchronously to adjacent devices when no test operation of the device is
needed at the board level. The waveforms in
through a device after the TAP controller is in the SHIFT_DR state. In this state, data
signals are clocked into the bypass register from TDI on the rising edge of TCK and
out of TDO on the falling edge of the same clock pulse.
EXIT1_IR
UPDATE_IR
SELECT_DR_SCAN
CAPTURE_DR
Bit 1
Bit 2
Bit 1
SHIFT_DR
Bit 3
Bit 2
Figure 13–12
(1)
Bit 4
show how scan data passes
Stratix III Device Handbook, Volume 1
EXIT1_DR
UPDATE_DR
13–15