EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 414

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

13–16
IDCODE Instruction Mode
Table 13–5. 32-Bit Stratix III Device IDCODE
USERCODE Instruction Mode
CLAMP Instruction Mode
Stratix III Device Handbook, Volume 1
EP3SL50
EP3SL70
EP3SL110
EP3SL150ES
EP3SL150
EP3SL200
EP3SL340
EP3SE50
EP3SE80
EP3SE110
EP3SE260
Notes to
(1) The most significant bit (MSB) is on the left.
(2) The IDCODE’s least significant bit (LSB) is always 1.
Device
Table
13–5:
1
Version (4 Bits)
Use the IDCODE instruction mode to identify the devices in an IEEE Std. 1149.1 chain.
When IDCODE is selected, the device identification register is loaded with the 32-bit
vendor-defined identification code. The device ID register is connected between the
TDI and TDO ports, and the device IDCODE is shifted out.
information for Stratix III devices.
Use the USERCODE instruction mode to examine the user electronic signature (UES)
within the devices along an IEEE Std. 1149.1 chain. When you select this instruction,
the device identification register is connected between the TDI and TDO ports. The
user-defined UES is shifted into the device ID register in parallel from the 32-bit
USERCODE register. The UES is then shifted out through the device ID register.
The UES value is not user defined until after the device is configured. This value is
stored in the programmer object file (.pof) and only loaded to the device during
configuration. Before configuration, the UES value is set to the default value.
Use the CLAMP instruction mode to allow the state of the signals driven from the pins
to be determined from the boundary-scan register while the bypass register is selected
as the serial path between the TDI and TDO ports. The states of all signals driven from
the pins are completely defined by the data held in the boundary-scan register.
0000
0000
0001
0000
0001
0000
0000
0000
0000
0000
0000
Part Number (16 Bits)
0010 0001 0000 1000
0010 0001 0000 0001
0010 0001 0000 1001
0010 0001 0000 0010
0010 0001 0000 0011
0010 0001 0000 0101
0010 0001 0000 0110
0010 0001 0000 1010
0010 0001 0000 0111
0010 0001 0000 0100
0010 0001 0000 0010
Chapter 13: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices
IDCODE (32 Bits)
Manufacturer Identity (11 Bits)
(1)
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
IEEE Std. 1149.1 BST Operation Control
Table 13–5
© July 2010 Altera Corporation
lists the IDCODE
(1 Bit)
LSB
1
1
1
1
1
1
1
1
1
1
1
(2)