EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 415

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 13: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices
I/O Voltage Support in JTAG Chain
HIGHZ Instruction Mode
I/O Voltage Support in JTAG Chain
© July 2010
Altera Corporation
The HIGHZ instruction mode sets all of the user I/O pins to an inactive drive state.
These pins are tri-stated until a new JTAG instruction is executed. When this
instruction is loaded into the instruction register, the bypass register is connected
between the TDI and TDO ports.
The JTAG chain supports several devices. However, you should use caution if the
chain contains devices that have different V
TDO pin must meet the specifications of the TDI pin it drives. The TDI and TDO pins of
Stratix III device are powered by the V
should connect V
I/O standards, you should connect V
connect V
2.5 V.
operation.
Table 13–6. Supported TDO/TDI Voltage Combinations
You can interface the TDI and TDO lines of the devices that have different V
by inserting a level shifter between the devices. If possible, you should build the JTAG
chain in such a way that a device with a higher V
equal or lower V
a level acceptable to the JTAG tester.
voltages and how a level shifter is inserted in the chain.
Stratix III
Non-Stratix III
Notes to
(1) The TDO output buffer meets V
(2) The TDO output buffer meets V
(3) Input buffer must be 3.3-V tolerant.
(4) Input buffer must be 3.0-V tolerant.
(5) Input buffer must be 2.5-V tolerant.
Device
Table 13–6
Table
CCPD
13–6:
to 3.0 V; for 2.5-V and below I/O standards, you should connect V
V
V
V
V
V
V
V
TDI Input Buffer Power
CCIO
CCPD
CCPD
CCPD
CC
CC
CC
CC
lists board design recommendations to ensure proper JTAG chain
CCPD
= 3.3 V
= 2.5 V
= 1.8 V
= 1.5 V
= 3.3V
= 3.0V
= 2.5V
level. This way, a level shifter is used only to shift the TDO level to
according to the I/O standard used in the same bank. For 3.3-V
OH
OH
(MIN) = 2.4 V.
(MIN) = 2.0 V.
CCPD
Figure 13–13
CCPD
V
C CP D
to 3.3 V. For 3.0-V I/O standards, you should
v
v
v
v
(2.5 V / 3.0 V / 3.3 V) of I/O Bank 1A. You
= 3.3 V
CCIO
v
v
v
(3)
(3)
(3)
(3)
levels. The output voltage level of the
(1)
CCIO
shows the JTAG chain of mixed
level drives to a device with an
Stratix III TDO V
V
C CP D
v
v
v
v
Stratix III Device Handbook, Volume 1
= 3.0 V
v
v
v
(4)
(4)
(4)
(4)
(1)
C CPD
V
CC PD
v
v
v
v
= 2.5 V
CCIO
v
v
v
(5)
(5)
(5)
(5)
CCPD
levels
13–17
(2)
to