EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 424
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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14–2
Security Against Reverse Engineering
Security Against Tampering
AES Decryption Block
Flexible Security Key Storage
Stratix III Device Handbook, Volume 1
f
Reverse engineering from an encrypted configuration file is very difficult and time
consuming because the Stratix III configuration file formats are proprietary and the
file contains million of bits which require specific decryption. Reverse engineering the
Stratix III device is just as difficult because the device is manufactured on the most
advanced 65-nm process technology.
The non-volatile keys are one-time programmable. Once the tamper protection bit is
set in the key programming file generated by the Quartus
device can only be configured with configuration files encrypted with the same key.
For more information about why this feature is secured, refer to the
Stratix III Devices
The main purpose of the AES decryption block is to decrypt the configuration
bitstream prior to entering data decompression or configuration.
Prior to receiving encrypted data, you must enter and store the 256-bit security key in
the device. You can choose between a non-volatile security key and a volatile security
key with battery backup.
The security key is scrambled prior to storing it in key storage in order to make it
more difficult for anyone to retrieve the stored key using de-capsulation of the device.
Stratix III devices support two types of security key programming: volatile and
non-volatile.
keys.
Table 14–1. Security Keys Options
You can program the non-volatile key to the Stratix III device without an external
battery. Also, there are no additional requirements to any of the Stratix III power
supply inputs.
Key programmability
External battery
Key programming method
Design protection
Note to
(1) Key programming is carried out using JTAG interface.
Table
Options
14–1:
Table 14–1
white paper.
(1)
shows the differences between volatile keys and non-volatile
Reprogrammable and erasable
Required
On-board
Secure against copying and
reverse engineering
Volatile Key
Chapter 14: Design Security in Stratix III Devices
®
One-time programmable
Not required
On and off board
Secure against copying and
reverse engineering. Tamper
resistant if tamper protection
bit is set.
II software, the Stratix III
© May 2009 Altera Corporation
Non-Volatile Key
Design Security in
AES Decryption Block
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