EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 435
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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Chapter 15: SEU Mitigation in Stratix III Devices
User Mode Error Detection
Table 15–2. Fault Injection Register and Error Injection
Automated Single Event Upset Detection
© March 2010 Altera Corporation
Content
Note to
(1) Bit[20] and Bit[19] cannot both be set to 1 as this is not a valid selection. The error detection circuitry decodes it as no error injection.
Description
Bit
Table
15–2:
1
Bit[20]
Error Type
0
1
0
Table 15–2
injection.
After the test completes, Altera recommends that you reconfigure the device.
Stratix III devices offer on-chip circuitry for automated checking of single-event upset
detection. Some applications that require the device to operate error-free in
high-neutron flux environments require periodic checks to ensure continued data
integrity. The error detection CRC feature ensures data reliability and is one of the
best options for mitigating SEU.
You can implement the error detection CRC feature with existing circuitry in
Stratix III devices, eliminating the need for external logic. The CRC_ERROR pin reports
a soft error when configuration CRAM data is corrupted and you would have to
decide whether to reconfigure the device or to ignore the error.
Bit[19]
(1)
1
0
0
lists how the fault injection register is implemented and describes error
Error Injection Type
Single byte error injection
Double-adjacent byte error injection
No error injection
Bit[20..19]
Error Type
Depicts the location
of the injected error
in the first data
frame.
the Injected Error
Byte Location of
Bit[18..8]
Stratix III Device Handbook, Volume 1
Depicts the location
of the bit error and
corresponds to the
error injection type
selection.
Error Byte Value
Bit[7..0]
15–5
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