EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 437

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 15: SEU Mitigation in Stratix III Devices
Error Detection Block
Error Detection Block
Error Detection Registers
© March 2010 Altera Corporation
1
You can enable the Stratix III device error detection block in the Quartus II software
(refer
calculate the 16-bit CRC signature for the configuration CRAM bits in the device.
The CRC circuit continues running even if an error occurs. When a soft error occurs,
the device sets the CRC_ERROR pin high. Two types of CRC detection check the
configuration bits:
■
The
when the device is in user mode.
■
There is one set of 16-bit registers in the error detection circuitry that stores the
computed CRC signature. A non-zero value on the syndrome register causes the
CRC_ERROR pin to be set high.
detection circuitry, syndrome registers, and error injection block.
The CRAM error checking ability (16-bit CRC) during user mode, for use by the
CRC_ERROR pin.
■
■
■
■
■
The 16-bit CRC that is embedded in every configuration data frame.
■
■
“Error Detection Registers”
to“Software Support” on page
For each frame of data, the pre-calculated 16-bit CRC enters the CRC circuit
right at the end of the frame data and determines whether or not there is an
error.
If an error occurs, the search engine starts to find the location of the error.
You can shift the error messages out through the JTAG instruction or core
interface logic while the error detection block continues running.
The JTAG interface reads out the 16-bit CRC result for the first frame and also
shifts the 16-bit CRC bits to the 16-bit CRC storage registers for test purposes.
You can deliberately introduce single error, double errors, or double errors
adjacent to each other to configuration memory for testing and design
verification.
During configuration, after a frame of data is loaded into the Stratix III device,
the pre-computed CRC is shifted into the CRC circuitry.
At the same time, the CRC value for the data frame shifted-in is calculated. If
the pre-computed CRC and calculated CRC values do not match, nSTATUS is
set low. Every data frame has a 16-bit CRC; therefore, there are many 16-bit
CRC values for the whole configuration bitstream. Every device has different
lengths of the configuration data frame.
Figure 15–1
section focuses on the first type, the 16-bit CRC only
15–11). This block contains the logic necessary to
shows the block diagram of the error
Stratix III Device Handbook, Volume 1
15–7