EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 439

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 15: SEU Mitigation in Stratix III Devices
Error Detection Timing
Table 15–4. Error Detection Registers (Part 2 of 2)
Error Detection Timing
Table 15–5. Minimum and Maximum Error Detection Frequencies
© March 2010 Altera Corporation
JTAG Shift Register
User Shift Register
JTAG Fault Injection
Register
Fault Injection Register
Device Type
Stratix III
Register
1
Error Detection
100 MHz / 2
When the CRC feature is enabled through the Quartus II software, the device
automatically activates the CRC process upon entering user mode, after
configuration, and after initialization is complete.
If an error is detected within a frame, CRC_ERROR is driven high at the end of the error
location search, and after the Error Message Register gets updated. At the end of this
cycle, the CRC_ERROR pin is pulled low for a minimum 32 clock cycles. If the next
frame also contains an error, the CRC_ERROR is driven high again after the Error
Message Register gets overwritten by the new value. You can start to unload the error
message on each rising edge of CRC_ERROR pin. The error detection runs until the
device is reset.
Error detection circuitry runs off an internal configuration oscillator with a divisor
that sets the maximum frequency.
detection frequencies.
You can set a lower clock frequency by specifying a division factor in the Quartus II
software (refer to
(2), where n is between 1 and 8. The divisor ranges from 2 through 256. Refer to
Equation
Equation 15–1.
The error detection frequency reflects the frequency of the error detection process for
a frame because the CRC calculation in Stratix III devices is done on a per-frame basis.
Frequency
This register is accessible by the JTAG interface and allows the contents of the JTAG Update
Register to be sampled and read out by the JTAG instruction SHIFT_EDERROR_REG.
This register is accessible by the core logic and allows the contents of the User Update Register to
be sampled and read by the user logic.
This 21-bit register is fully controlled by the JTAG instruction EDERROR_INJECT. This register
holds the information of the error injection that you want in the bitstream.
The content of the JTAG Fault Injection Register is loaded in this 21-bit register when it is being
updated.
15–1.
n
Detection Frequency
“Software Support” on page
Maximum Error
50 MHz
Error detection frequency
Table 15–5
Description
Minimum Error Detection
lists the minimum and maximum error
Frequency
390 kHz
15–11). The divisor is a power of two
=
100MHz
------------------- -
2
n
Stratix III Device Handbook, Volume 1
Valid Exponents (n)
1, 2, 3, 4, 5, 6, 7, 8
15–9