EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 440

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

15–10
Stratix III Device Handbook, Volume 1
You must monitor the error message to avoid missing information in the Error
Message Register. The Error Message Register is updated whenever an error occurs.
The minimum interval time between each update for the Error Message Register
depends on the device and the error detection clock frequency.
estimated minimum interval time between each update for the Error Message
Register for Stratix III devices.
Table 15–6. Minimum Update Interval for Error Message Register
The CRC calculation time for the error detection circuitry to check from the first until
the last frame depends on the device and the error detection clock frequency.
Table 15–7
maximum clock frequencies for Stratix III devices. The minimum CRC calculation
time is calculated by using the maximum error detection frequency with divisor factor
1 while the maximum CRC calculation time is calculated by using the minimum error
detection frequency with divisor factor 8.
Table 15–7. CRC Calculation Time
Note to
(1) These timing numbers are preliminary.
Table
EP3SL110
EP3SL150
EP3SL200
EP3SL260
EP3SL340
EP3SE110
EP3SL50
EP3SL70
EP3SE50
EP3SE80
lists the estimated time for each CRC calculation with minimum and
Device
15–6:
EP3SL110
EP3SL150
EP3SL200
EP3SE260
EP3SL340
EP3SE110
EP3SL50
EP3SL70
EP3SE50
EP3SE80
Device
Minimum Time (ms)
110.00
110.00
212.00
212.00
270.00
113.00
113.00
52.00
52.00
59.00
Chapter 15: SEU Mitigation in Stratix III Devices
Timing Interval (μs)
(Note 1)
© March 2010 Altera Corporation
14.8
14.8
19.8
19.8
21.8
14.8
14.8
Table 15–6
9.8
9.8
9.8
Maximum Time (s)
14.36
14.36
30.38
30.38
58.72
58.72
74.87
16.41
31.28
31.28
Error Detection Timing
lists the