EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 447

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 16: Programmable Power and Temperature-Sensing Diodes in Stratix III Devices
Stratix III External Power Supply Requirements
Relationship Between Selectable Core Voltage and Programmable Power Technology
Stratix III External Power Supply Requirements
© February 2009 Altera Corporation
With programmable power technology, faster speed grade FPGAs may require less
power, as there are fewer high-speed MLAB and LAB pairs, compared to slower
speed grade FPGAs. The slower speed grade device may need to use more high-speed
MLAB and LAB pairs to meet the performance requirements, while the faster speed
grade device can meet the performance requirements with MLAB and LAB pairs in
low-power mode.
The Quartus II software sets unshared inputs and unused device resources in the
design to low-power mode to reduce static and dynamic power. The Quartus II
software sets the following resources to low power when they are not used in the
design:
■
■
■
■
■
■
If the PLL is instantiated in the design, asserting a reset high keeps the PLL in low
power.
Table 16–1
speed grade considerations to the permutations to give you flexibility in designing
your system.
Table 16–1. Stratix III Programmable Power Capabilities
This section describes the different external power supplies needed to power
Stratix III devices.
devices. Some of the power supply pins can be supplied with the same external power
supply, provided they need the same voltage level, as noted in the recommended
board connection column.
LAB
Routing
Memory Blocks
DSP Blocks
Global Clock Networks
I/O Elements (IOE)
Note to
(1) Tiles with DSP blocks, memory blocks, and I/O elements that are used in the design are always set to high-speed
LABs and MLABs
TriMatrix memory blocks
External memory interface circuitry
DSP blocks
phase-locked loop (PLL)
serializer/deserializer (SERDES) and DPA blocks
mode. Unused DSP blocks, memory blocks, and I/O interfaces are set to low-power mode by default.
Table
shows available Stratix III programmable power capabilities. You can
16–1:
Table 16–2
lists the external power supply pins for Stratix III
Selectable Core Voltage
Yes
Yes
Yes
Yes
Yes
No
Stratix III Device Handbook, Volume 1
Programmable Power
Fixed setting
Fixed setting
Fixed setting
Technology
Yes
Yes
No
(1)
(1)
(1)
16–3