EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 49
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices
Adaptive Logic Modules
Figure 2–4. LAB-Wide Control Signals
Adaptive Logic Modules
© February 2009 Altera Corporation
Dedicated Row LAB Clocks
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
The basic building block of logic in the Stratix III architecture, the adaptive logic
module (ALM), provides advanced features with efficient logic utilization. Each ALM
contains a variety of look-up table (LUT)-based resources that can be divided between
two combinational adaptive LUTs (ALUTs) and two registers. With up to eight inputs
to the two combinational ALUTs, one ALM can implement various combinations of
two functions. This adaptability allows an ALM to be completely backward-
compatible with four-input LUT architectures. One ALM can also implement any
function of up to six inputs and certain seven-input functions.
In addition to the adaptive LUT-based resources, each ALM contains two
programmable registers, two dedicated full adders, a carry chain, a shared arithmetic
chain, and a register chain. Through these dedicated resources, an ALM can efficiently
implement various arithmetic functions and shift registers. Each ALM drives all types
of interconnects: local, row, column, carry chain, shared arithmetic chain, register
chain, and direct link interconnects.
the Stratix III ALM while
ALM.
6
6
6
labclk0
clock signals per LAB.
There are two unique
or asyncload
or labpreset
labclkena0
Figure 2–6
labclk1
Figure 2–5
shows a detailed view of all the connections in an
labclkena1
shows a high-level block diagram of
labclk2
labclkena2
Stratix III Device Handbook, Volume 1
syncload
labclr0
labclr1
synclr
2–5
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