EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 54

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

2–10
Figure 2–8. 4 × 2 Crossbar Switch Example
Stratix III Device Handbook, Volume 1
sel0[1..0]
sel1[1..0]
inputa
inputb
inputc
inputd
In the case of implementing 2 six-input functions in one ALM, four inputs must be
shared and the combinational function must be the same. For example, a 4 × 2
crossbar switch (two 4-to-1 multiplexers with common inputs and unique select lines)
can be implemented in one ALM, as shown in
dataa, datab, datac, and datad, while the unique select lines are datae0 and
dataf0 for function0, and datae1 and dataf1 for function1. This crossbar
switch consumes four LUTs in a four-input LUT-based architecture.
In a sparsely used device, functions that could be placed into one ALM may be
implemented in separate ALMs by the Quartus II software in order to achieve the best
possible performance. As a device begins to fill up, the Quartus II software
automatically utilizes the full potential of the Stratix III ALM. The Quartus II
Compiler automatically searches for functions of common inputs or completely
independent functions to be placed into one ALM and to make efficient use of the
device resources. In addition, you can manually control resource usage by setting
location assignments.
Any six-input function can be implemented utilizing inputs dataa, datab, datac,
datad, and either datae0 and dataf0 or datae1 and dataf1. If datae0 and
dataf0 are utilized, the output is driven to register0, and/or register0 is
bypassed and the data drives out to the interconnect using the top set of output
drivers (refer to
register1 and/or bypasses register1 and drives to the interconnect using the
bottom set of output drivers. The Quartus II Compiler automatically selects the inputs
to the LUT. ALMs in normal mode support register packing.
4 × 2 Crossbar Switch
Figure
out0
out1
2–9). If datae1 and dataf1 are utilized, the output drives to
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices
datae0
datae1
dataf0
dataf1
dataa
datab
datad
datac
Implementation in 1 ALM
(Function0)
(Function1)
Figure
Six-Input
Six-Input
LUT
LUT
2–8. The shared inputs are
© February 2009 Altera Corporation
combout0
combout1
Adaptive Logic Modules