EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 60

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

2–16
Figure 2–14. Example of a 3-Bit Add Utilizing Shared Arithmetic Mode
Stratix III Device Handbook, Volume 1
3-Bit Add Example
3-Bit Add Example
1
1
in LUTs.
in LUTs.
2
2
in s.
in s.
st
st
nd
nd
stage add is implemented
stage add is implemented
stage add is implemented
stage add is implemented
+ 1 1 0 0
1 1 1 1 1
+ 1 1 0 1
Binary Add
0 1 1 1
1 1 1 0
0 1 0 0
Shared Arithmetic Chain
The shared arithmetic chain available in enhanced arithmetic mode allows the ALM
to implement a three-input add. This significantly reduces the resources necessary to
implement large adder trees or correlator functions.
The shared arithmetic chains can begin in either the first or sixth ALM in an LAB. The
Quartus II Compiler creates shared arithmetic chains longer than 20 (10 ALMs in
arithmetic or shared arithmetic mode) by linking LABs together automatically. For
enhanced fitting, a long shared arithmetic chain runs vertically allowing fast
horizontal connections to TriMatrix memory and DSP blocks. A shared arithmetic
chain can continue as far as a full column.
Similar to the carry chains, the top and bottom half of shared arithmetic chains in
alternate LAB columns can be bypassed. This capability allows the shared arithmetic
chain to cascade through half of the ALMs in a LAB while leaving the other half
available for narrower fan-in functionality. Every other LAB column is top-half
bypassable, while the other LAB columns are bottom-half bypassable.
+ C3 C2 C1 C0
+ 2 x 12
Decimal
Equivalents
R4 R3 R2 R1 R0
+
+ 13
X3 X2 X1 X0
Y3 Y2 Y1 Y0
S3 S2 S1 S0
14
Z3 Z2 Z1 Z0
31
7
4
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices
X3
Y3
Z3
X0
Y0
X1
Y1
X2
Y2
Z0
Z1
Z2
ALM Implementation
ALM 1
ALM 2
3-Input
3-Input
3-Input
3-Input
3-Input
3-Input
3-Input
3-Input
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
© February 2009 Altera Corporation
S0
C0
S1
C1
S2
C2
S3
C3
shared_arith_in = '0'
Adaptive Logic Modules
carry_in = '0'
R2
R3
R4
R0
R1