EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 64

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

2–20
ALM Interconnects
Figure 2–18. Shared Arithmetic Chain, Carry Chain, and Register Chain Interconnects
Clear and Preset Logic Control
Stratix III Device Handbook, Volume 1
f
There are three dedicated paths between ALMs: Register Cascade, Carry-chain, and
Shared Arithmetic chain. Stratix III devices include an enhanced interconnect
structure in LABs for routing shared arithmetic chains and carry chains for efficient
arithmetic functions. The register chain connection allows the register output of one
ALM to connect directly to the register input of the next ALM in the LAB for fast shift
registers. These ALM-to-ALM connections bypass the local interconnect. The
Quartus II Compiler automatically takes advantage of these resources to improve
utilization and
chain, and register chain interconnects.
For information about routing between LABs, refer to the
Stratix III Devices
LAB-wide signals control the logic for the register's clear signal. The ALM directly
supports an asynchronous clear function. You can achieve the register preset through
the Quartus II software’s NOT-gate push-back logic option. Each LAB supports up to
two clears.
Stratix III devices provide a device-wide reset pin (DEV_CLRn) that resets all registers
in the device. An option set before compilation in the Quartus II software controls this
pin. This device-wide reset overrides all other control signals.
routing to adjacent ALM
Carry chain & shared
arithmetic chain
interconnect
performance.Figure 2–18
chapter in volume 1 of the Stratix III Device Handbook.
Local
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices
Local interconnect
routing among ALMs
in the LAB
ALM 10
ALM 1
ALM 2
ALM 3
ALM 4
ALM 5
ALM 6
ALM 7
ALM 8
ALM 9
shows the shared arithmetic chain, carry
Register chain
routing to adjacent
ALM's register input
MultiTrack Interconnect in
© February 2009 Altera Corporation
Adaptive Logic Modules