EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 69

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 3: MultiTrack Interconnect in Stratix III Devices
Column Interconnects
© October 2008 Altera Corporation
Stratix III devices include an enhanced interconnect structure in LABs for
routing-shared arithmetic chains and carry chains for efficient arithmetic functions.
The register chain connection allows the register output of one ALM to connect
directly to the register input of the next ALM in the LAB for fast shift registers. These
ALM-to-ALM connections bypass the local interconnect. The Quartus II Compiler
automatically takes advantage of these resources to improve utilization and
performance.
chain interconnects.
Figure 3–2. Shared Arithmetic Chain, Carry Chain, and Register Chain Interconnects
The C4 interconnects span four adjacent interfaces in the same device column. C4
interconnects also pass by M144K and DSP blocks. A single M144K block utilizes
eight adjacent interfaces in the same column. A DSP block utilizes four adjacent
interfaces in the same column.
a LAB in a column. The C4 interconnects can drive and be driven by all types of
architecture blocks, including DSP blocks, TriMatrix memory blocks, and column and
row IOEs. For LAB interconnection, a primary LAB or its LAB neighbor can drive a
given C4 interconnect. C4 interconnects can drive each other to extend their range as
well as drive row interconnects for column-to-column connections.
Figure 3–2
Routing to Adjacent ALM
Carry Chain & Shared
Arithmetic Chain
shows the shared arithmetic chain, carry chain, and register
Interconnect
Local
Figure 3–3
Local Interconnect
Routing Among ALMs
in the LAB
shows the C4 interconnect connections from
ALM10
ALM 1
ALM 2
ALM 3
ALM 4
ALM 5
ALM 6
ALM 7
ALM 8
ALM 9
Register Chain
Routing to Adjacent
ALM's Register Input
Stratix III Device Handbook, Volume 1
3–3