EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 72

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

3–6
Memory Block Interface
Stratix III Device Handbook, Volume 1
The R4 and C4 interconnects provide superior and flexible routing capabilities.
Stratix III has a three-sided routing architecture which allows the interconnect wires
from each LAB to reach the adjacent LABs to its right and left. A given LAB can drive
32 other LABs using one R4 or C4 interconnect, in one hop. This routing scheme
improves efficiency and flexibility by placing all the critical LABs within one hop of
the routing interconnects.
Table 3–2
the R4 and C4 interconnects.
Table 3–2. Number of LABs reachable using C4 and R4 interconnects
TriMatrix memory consists of three types of RAM blocks: MLAB, M9K, and M144K.
This section provides a brief overview of how the different memory blocks interface to
the routing structure.
The RAM blocks in Stratix III devices have local interconnects to allow ALMs and
interconnects to drive into RAM blocks. The MLAB RAM block local interconnect is
driven by the R4, C4, and direct link interconnects from adjacent LABs. The MLAB
RAM blocks can communicate with LABs on either the left or right side through these
row interconnects or with LAB columns on the left or right side with the column
interconnects. Each MLAB RAM block has up to 20 direct link input connections from
the left adjacent LAB and another 20 from the right adjacent LAB. MLAB RAM
outputs can also connect to left and right LABs through a direct link interconnect. The
MLAB RAM block has equal opportunity for access and performance to and from
LABs on either its left or right side.
row interface.
shows how many LABs are reachable within one, two, or three hops using
Hops
1
2
3
Figure 3–4
Chapter 3: MultiTrack Interconnect in Stratix III Devices
shows the MLAB RAM block to LAB
Number of LABs
© October 2008 Altera Corporation
160
34
96
Memory Block Interface