EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 83

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices
Overview
Table 4–2. TriMatrix Memory Capacity and Distribution in Stratix III Devices
TriMatrix Memory Block Types
Parity Bit Support
Byte-Enable Support
© May 2009 Altera Corporation
EP3SL50
EP3SL70
EP3SL110
EP3SL150
EP3SL200
EP3SL340
EP3SE50
EP3SE80
EP3SE110
EP3SE260
Note to
(1) For total ROM Kbits, use this equation to calculate:
Total ROM Kbits = Total Embedded RAM Kbits + [(number of MLAB blocks × 640)/1024]
Device
Table
4–2:
1
1
MLABs
1,350
2,150
2,850
4,000
6,750
1,600
2,150
5,100
Table 4–2
each Stratix III family member
950
950
While the M9K and M144K memory blocks are dedicated resources, the MLABs are
dual-purpose blocks. They can be configured as regular logic array blocks (LABs) or
as memory logic array blocks (MLABs). Ten adaptive logic modules (ALMs) make up
one MLAB. Each ALM in an MLAB can be configured as a 16 × 2 block, resulting in a
16 × 20 simple dual-port SRAM block in a single MLAB. In ROM mode, each ALM in
an MLAB can be configured as either a 64 × 1 or a 32 × 2 block, resulting in a 64 × 10
or 32 × 20 ROM block in a single MLAB.
All the ALMs share the same address bits. Therefore, you cannot combine multiple
memories with different address bits and implement them in a single MLAB.
When you are using an MLAB as memory, you will not be able to use the unused
ALMs in the MLAB even if you do not use the full capacity of an MLAB.
All TriMatrix memory blocks have built-in parity-bit support. The ninth bit associated
with each byte can store a parity bit or serve as an additional data bit. No parity
function is actually performed on the ninth bit.
All TriMatrix memory blocks support byte-enables that mask the input data so that
only specific bytes of data are written. The unwritten bytes retain the previous written
value. The write enable (wren) signals, along with the byte-enable (byteena) signals,
control the RAM blocks’ write operations.
shows the capacity and distribution of the TriMatrix memory blocks for
Blocks
1,040
M9K
108
150
275
355
468
400
495
639
864
M144K
Blocks
12
16
36
48
12
12
16
48
6
6
(dedicated memory blocks
Total Dedicated RAM Bits
16,272 Kb
14,688 Kb
1,836 Kb
2,214 Kb
4,203 Kb
5,499 Kb
9,396 Kb
5,328 Kb
6,183 Kb
8,055 Kb
only)
Stratix III Device Handbook, Volume 1
Total RAM Bits (including
MLABs)
10,646 Kb
18,381 Kb
16,282 Kb
2,133 Kb
2,636 Kb
4,875 Kb
6,390 Kb
5,625 Kb
6,683 Kb
8,727 Kb
(1)
4–3