EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 85

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices
Overview
Figure 4–2. Stratix III Byte-Enable Functional Waveform for MLABs
Packed Mode Support
Address Clock Enable Support
© May 2009 Altera Corporation
current data: q (asynch)
contents at a1
contents at a0
contents at a2
address
byteena
inclock
wren
data
Figure 4–2
control the operations of the MLABs. The write operation in MLABs is triggered by
failing clock edges.
Stratix III M9K and M144K blocks support packed mode. The packed mode feature
packs two independent single-port RAMs into one memory block. The Quartus II
software automatically implements packed mode where appropriate by placing the
physical RAM block into true dual-port mode and using the MSB of the address to
distinguish between the two logical RAMs. The size of each independent single-port
RAM must not exceed half of the target block size.
All Stratix III memory blocks support address clock enable, which holds the previous
address value for as long as the signal is enabled (addressstall = 1). When the
memory blocks are configured in dual-port mode, each port has its own independent
address clock enable. The default value for the address clock enable signals is low
(disabled).
XXXX
an
XX
doutn
FFFF
FFFF
shows how the write enable (wren) and byte-enable (byteena) signals
FFFF
a0
10
FFFF
ABFF
ABCD
FFFF
a1
01
FFCD
FFFF
a2
11
ABFF
ABCD
a0
ABFF
FFCD
Stratix III Device Handbook, Volume 1
ABCD
a1
XXXX
XX
FFCD
a2
FFCD
4–5