EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 88

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

4–8
Figure 4–6. Stratix III Address Clock Enable during Write Cycle Waveform for MLABs
Mixed Width Support
Asynchronous Clear
Stratix III Device Handbook, Volume 1
1
1
latched address
(inside memory)
contents at a0
contents at a1
contents at a2
contents at a3
contents at a4
contents at a5
addressstall
wraddress
Figure 4–6
MLABs.
M9K and M144K memory blocks inherently support mixed data widths. MLABs can
support mixed data widths through emulation via the Quartus II software. When
using simple dual-port or true dual-port mixed width support allows you to read and
write different data widths to a memory block. Refer to
page 4–10
You cannot use the ECC on M144 memory blocks when using the mixed width
support.
MLABs do not support mixed-width FIFO mode.
Stratix III M9K and M144K memory blocks support asynchronous clears on the
output latches and output registers. MLABs supports asynchronous clear on the
output registers only as the output is not latched. Therefore, if your M9K and M144K
are not using the output registers, you can still clear the RAM outputs via the output
latch asynchronous clear. The functional waveform in
functionality.
inclock
wren
data
an
for details on the different widths supported per memory mode.
shows the address clock enable waveform during the write cycle for
XX
a0
00
a0
XX
a1
01
XX
01
02
a2
XX
Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices
a1
XX
XX
02
a3
03
00
a4
04
a4
Figure 4–7
“Memory Modes” on
03
05
a5
04
a5
© May 2009 Altera Corporation
shows this
05
a6
06
Overview