EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 93

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices
Overview
Table 4–5. Stratix III M9K Block Mixed-Width Configurations (Simple Dual-Port Mode)
Table 4–6. Stratix III M144K Block Mixed-Width Configurations (Simple Dual-Port Mode)
© May 2009 Altera Corporation
8K×1
4K×2
2K×4
1K×8
512×16
256×32
1K×9
512×18
256×36
16K×8
8K×16
4K×32
2K×64
16K×9
8K×18
4K×36
2K×72
Read Port
Read Port
Figure 4–12. Stratix III Simple Dual-Port Memory
Note to
(1) Simple dual-port RAM supports input/output clock mode in addition to the read/write clock mode shown.
Simple dual-port mode supports different read and write data widths (mixed width
support).
simple dual-port mode. MLABs do not have native support for mixed width
operation. The Quartus II software can implement mixed width memories in MLABs
by using more than one MLAB.
Table 4–6
dual-port mode.
8K×1
v
v
v
v
v
v
—
—
—
16K×8
v
v
v
v
—
—
—
—
Figure
4K×2
Table 4–5
shows the mixed width configurations for the M144K blocks in simple
v
v
v
v
v
v
—
—
—
4–12:
8K×16
v
v
v
v
—
—
—
—
2K×4
v
v
v
v
v
v
shows the mixed width configurations for the M9K blocks in
—
—
—
4K×32
v
v
v
v
—
—
—
—
1K×8
v
v
v
v
v
v
data[ ]
wraddress[ ]
wren
byteena[]
wr_addressstall
wrclock
wrclocken
aclr
—
—
—
2K×64
512×16
v
v
v
v
—
—
—
—
Write Port
v
v
v
v
v
v
—
—
—
Write Port
(Note 1)
16K×9
rd_addressstall
256×32
—
—
—
—
v
v
v
v
v
v
v
v
v
v
—
—
—
rdaddress[ ]
ecc_status
rdclocken
rdclock
rden
q[ ]
8K×18
1K×9
v
v
v
v
—
—
—
—
Stratix III Device Handbook, Volume 1
—
—
—
—
—
—
v
v
v
512×18
4K×36
—
—
—
—
—
—
v
v
v
—
—
—
—
v
v
v
v
256×36
2K×72
v
v
v
v
v
v
v
—
—
—
—
—
—
—
—
—
—
4–13