EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 96

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

4–16
Table 4–8. Stratix III M144K Block Mixed-Width Configurations (True Dual-Port Mode)
Stratix III Device Handbook, Volume 1
16K×8
8K×16
4K×32
16K×9
8K×18
4K×36
Read Port
Table 4–8
dual-port mode.
In true dual-port mode, M9K and M144K blocks support separate write-enable and
read-enable signals. You can save power by keeping the read-enable signal low
(inactive) when not reading. Read-during-write operations to the same address can
either output new data at that location or old data. To choose the desired behavior, set
the read-during-write behavior to either new data or old data in the RAM
MegaWizard Plug-In Manager in the Quartus II software. See
on page 4–21
In true dual-port mode you can access any memory location at any time from either
port. When accessing the same memory location from both ports, you must avoid
possible write conflicts. A write conflict happens when you attempt to write to the
same address location from both ports at the same time. This results in unknown data
being stored to that address location. No conflict resolution circuitry is built into the
Stratix III TriMatrix memory blocks. You must handle address conflicts external to the
RAM block.
Figure 4–16
port A and read operation at port B with the Read-During-Write behavior set to new
data. Registering the RAM’s outputs would simply delay the q outputs by one clock
cycle.
lists the possible M144K block mixed-port width configurations in true
16K×8
shows the true dual-port timing waveforms for the write operation at
v
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for more details about this behavior.
8K×16
v
v
v
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Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices
4K×32
v
v
v
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Write Port
16K×9
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v
v
v
© May 2009 Altera Corporation
“Read During Write”
8K×18
v
v
v
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4K×36
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v
v
v
Overview