EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 98
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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4–18
Figure 4–17. Stratix III Shift-Register Memory Configuration
ROM Mode
FIFO Mode
Stratix III Device Handbook, Volume 1
f
1
w × m × n Shift Register
W
W
W
W
Figure 4–17
All Stratix III TriMatrix memory blocks support ROM mode. A .mif file initializes the
ROM content of these blocks. The address lines of the ROM are registered on M9K
and M144K blocks, but can be unregistered on MLABs. The outputs can be registered
or unregistered. Output registers can be asynchronously cleared. The ROM read
operation is identical to the read operation in the single-port RAM configuration.
All TriMatrix memory blocks support FIFO mode. MLABs are ideal for designs with
many small, shallow FIFO buffers. To implement FIFO buffers in your design, use the
Quartus II software FIFO MegaWizard Plug-In Manager. Both single and dual-clock
(asynchronous) FIFOs are supported.
For more information about implementing FIFO buffers, refer to the
Dual-Clock FIFO Megafunctions User
MLABs do not support mixed-width FIFO mode.
m-Bit Shift Register
m-Bit Shift Register
m-Bit Shift Register
m-Bit Shift Register
shows the TriMatrix memory block in shift-register mode.
Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices
Guide.
W
W
W
W
© May 2009 Altera Corporation
n Number of Taps
Single- and
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