EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 99

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices
Clocking Modes
Clocking Modes
Independent Clock Mode
Input/Output Clock Mode
© May 2009 Altera Corporation
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1
1
Stratix III TriMatrix memory blocks support the following clocking modes:
■
■
■
■
Violating the setup or hold time on the memory block address registers could corrupt
the memory contents. This applies to both read and write operations.
Altera recommends using a memory block clock that comes through global clock
routing from an on-chip PLL set to 50% output duty cycle to achieve the maximum
memory block performance. Use Quartus II to report timing for this and other
memory block clocking schemes.
For more information refer to the
Table 4–9
Table 4–9. Stratix III TriMatrix Memory Clock Modes
Stratix III TriMatrix memory blocks can implement independent clock mode for true
dual-port memories. In this mode, a separate clock is available for each port (A and
B). Clock A controls all registers on the port A side, while clock B controls all registers
on the port B side. Each port also supports independent clock enables for port A and
port B registers. Asynchronous clears are supported only for output latches and
output registers on both ports.
Stratix III TriMatrix memory blocks can implement input/output clock mode for true
and simple dual-port memories. In this mode, an input clock controls all registers
related to the data input to the memory block, including data, address, byte-enables,
read enables, and write enables. An output clock controls the data output registers.
Asynchronous clears are available on output latches and output registers only.
Independent
Input/output
Read/write
Single clock
Clocking
Independent
Input/output
Read/write
Single clock
Mode
shows the clocking mode versus memory mode support matrix.
Dual-Port
Mode
True
v
v
v
—
Dual-Port
Simple
Mode
Stratix III Device Family Errata
v
v
v
—
Single-Port
Mode
v
v
—
—
Stratix III Device Handbook, Volume 1
ROM Mode
v
v
v
—
Sheet.
FIFO Mode
v
v
—
—
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