XC4VFX12-10FFG668C Xilinx Inc, XC4VFX12-10FFG668C Datasheet - Page 344

• Manufacturer Part Number: XC4VFX12-10FFG668C
• Description: IC FPGA VIRTEX-4 FX 12K 668FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-10FFG668C

• Total Ram Bits: 663552
• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 668-BBGA, FCBGA
• No. Of Logic Blocks: 12312
• No. Of Macrocells: 12312
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1591; XC4VFX12-10FFG668C

Chapter 7: SelectIO Logic Resources
344
There are two special cases:
1.
2.
Figure 7-16: Instantiate IDELAYCTRL without LOC Constraints - RDY Unconnected
REFCLK
When the RDY port is ignored, the RDY signals of all the replacement IDELAYCTRL
instances are left unconnected.
The VHDL and Verilog use models for instantiating an IDELAYCTRL primitive
without LOC constraints leaving the RDY output port unconnected are provided.
VHDL Use Model
-- Only one instance of IDELAYCTRL primitive is instantiated.
-- The RDY port is left open
dlyctrl:IDELAYCTRL
Verilog Use Model
// Only one instance of IDELAYCTRL primitive is instantiated.
// The RDY port is left open
IDELAYCTRL dlyctrl (
The resulting circuitry after instantiating the IDELAYCTRL components is illustrated
in
When RDY port is connected, an AND gate of width equal to the number of clock
regions is instantiated and the RDY output ports from the instantiated and replicated
IDELAYCTRL instances are connected to the inputs of the AND gate. The tools assign
the signal name connected to the RDY port of the instantiated IDELAYCTRL instance
to the output of the AND gate.
Figure
RST
7-16.
port map(
.
.
.
www.xilinx.com
.
.
.
);
RDY => open,
REFCLK => refclk,
RST => rst
);
.RDY(),
.REFCLK(refclk),
.RST(rst)
all IDELAYCTRL
Replicated for
Instantiated by user
REFCLK
RST
REFCLK
RST
REFCLK
RST
IDELAYCTRL
IDELAYCTRL
IDELAYCTRL
sites
.
.
.
RDY
RDY
RDY
Auto-generated by
mapper tool
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
RDY signal ignored
UG070_7_16_032008
R