XC4VFX12-10FFG668C Xilinx Inc, XC4VFX12-10FFG668C Datasheet - Page 360

• Manufacturer Part Number: XC4VFX12-10FFG668C
• Description: IC FPGA VIRTEX-4 FX 12K 668FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-10FFG668C

• Total Ram Bits: 663552
• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 668-BBGA, FCBGA
• No. Of Logic Blocks: 12312
• No. Of Macrocells: 12312
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1591; XC4VFX12-10FFG668C

Chapter 7: SelectIO Logic Resources
360
Timing Characteristics
Figure 7-26
Clock Event 1
•
•
Clock Event 4
At time T
case) becomes valid-High, resetting the output register and reflected at the Q output at
time T
CE
SR
D1
Q
C
At time T
High at the CE input of the output register, enabling the output register for incoming
data.
At time T
input of the output register and is reflected at the Q output at time T
Event 1.
RQ
OSRCK
after Clock Event 4.
illustrates the OLOGIC output register timing.
Figure 7-26: OLOGIC Output Register Timing Characteristics
OOCECK
ODCK
before Clock Event 4, the SR signal (configured as synchronous reset in this
before Clock Event 1, the output signal becomes valid-High at the D1
1
before Clock Event 1, the output clock enable signal becomes valid-
T
T
ODCK
OOCECK
www.xilinx.com
T
OCKQ
2
3
UG070 (v2.6) December 1, 2008
4
Virtex-4 FPGA User Guide
T
OSRCK
OCKQ
ug070_7_26_080204
after Clock
5
R