EP3C5F256C6 Altera, EP3C5F256C6 Datasheet - Page 62
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EP3C5F256C6
Manufacturer Part Number
EP3C5F256C6
Description
IC CYCLONE III FPGA 5K 256-FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
Specifications of EP3C5F256C6
Number Of Logic Elements/cells
5136
Number Of Labs/clbs
321
Total Ram Bits
423936
Number Of I /o
182
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-2418
EP3C5F256C6
EP3C5F256C6
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3C5F256C6
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP3C5F256C6N
Manufacturer:
ALTERA
Quantity:
5
Part Number:
EP3C5F256C6N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
2–18
Table 2–26. Cyclone III LS Devices RSDS Transmitter Timing Specification
Cyclone III Device Handbook, Volume 2
f
(input clock
frequency)
Device operation
in Mbps
t
TCCS
Output jitter
(peak to peak)
t
t
t
Notes to
(1) Applicable for true RSDS and Emulated RSDS with three-resistor network transmitters.
(2) True RSDS transmitter is only supported at the output pin of the Row I/O (Banks 1, 2, 5, and 6). Emulated RSDS with three-resistor network
(3) t
HSC LK
DUTY
RISE
FALL
LOC K
(3)
transmitter is supported at the output pin of all I/O banks.
LOC K
Symbol
Table
is the time required for the PLL to lock from the end of device configuration.
2–26:
Table 2–27. Cyclone III LS Devices Emulated RSDS with One-Resistor Network Transmitter Timing
Specifications
C
C
f
clock
frequency)
20 – 80%,
20 – 80%,
HSC LK
LOAD
LOAD
Modes
Symbol
×10
×10
×8
×7
×4
×2
×1
×8
×7
×4
×2
×1
—
—
—
—
= 5 pF
= 5 pF
(input
(Note 1)
Min
100
Modes
10
10
10
10
10
10
80
70
40
20
10
45
—
—
—
—
—
×10
×8
×7
×4
×2
×1
(Part 1 of 2) (Preliminary)
C7 and I7
500
500
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min
10
10
10
10
10
10
C7 and I7
155.5
155.5
155.5
155.5
155.5
Max
311
311
311
311
311
311
311
200
500
55
—
—
1
Typ
—
—
—
—
—
—
(Note
Max
170
Min
85
85
85
85
85
100
10
10
10
10
10
10
80
70
40
20
10
45
—
—
—
—
—
1),
(2)
Chapter 2: Cyclone III LS Device Data Sheet
Min
10
10
10
10
10
10
(Preliminary)
© December 2009 Altera Corporation
500
500
Typ
C8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Typ
C8
—
—
—
—
—
—
155.5
155.5
155.5
155.5
155.5
Switching Characteristics
Max
311
311
311
311
311
311
311
200
550
55
—
—
1
Max
170
85
85
85
85
85
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
Unit
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ms
ps
ps
ps
ps
%