EP2C8F256C7 Altera, EP2C8F256C7 Datasheet - Page 20
![IC CYCLONE II FPGA 8K 256-FBGA](/photos/6/70/67063/544-256-fbga_sml.jpg)
EP2C8F256C7
Manufacturer Part Number
EP2C8F256C7
Description
IC CYCLONE II FPGA 8K 256-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C8F256C7
Number Of Logic Elements/cells
8320
Number Of Labs/clbs
516
Total Ram Bits
165888
Number Of I /o
182
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-FBGA
Family Name
Cyclone® II
Number Of Logic Blocks/elements
8256
# I/os (max)
182
Frequency (max)
402.58MHz
Process Technology
90nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
8256
Ram Bits
165888
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1453
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2C8F256C7
Manufacturer:
ATI/AMD
Quantity:
1
Company:
Part Number:
EP2C8F256C7
Manufacturer:
ALTERA
Quantity:
1 045
Part Number:
EP2C8F256C7
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP2C8F256C7N
Manufacturer:
ALTERA
Quantity:
104
Part Number:
EP2C8F256C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Logic Array Blocks
Figure 2–6. Direct Link Connection
2–8
Cyclone II Device Handbook, Volume 1
Direct link interconnect from
block, embedded multiplier,
left LAB, M4K memory
PLL, or IOE output
interconnect
Direct link
to left
Interconnect
LAB Interconnects
The LAB local interconnect can drive LEs within the same LAB. The LAB
local interconnect is driven by column and row interconnects and LE
outputs within the same LAB. Neighboring LABs, PLLs, M4K RAM
blocks, and embedded multipliers from the left and right can also drive
an LAB’s local interconnect through the direct link connection. The direct
link connection feature minimizes the use of row and column
interconnects, providing higher performance and flexibility. Each LE can
drive 48 LEs through fast local and direct link interconnects.
shows the direct link connection.
LAB Control Signals
Each LAB contains dedicated logic for driving control signals to its LEs.
The control signals include:
■
■
■
■
■
Local
Two clocks
Two clock enables
Two asynchronous clears
One synchronous clear
One synchronous load
LAB
Direct link
interconnect
to right
Direct link interconnect from
right LAB, M4K memory
block, embedded multiplier,
PLL, or IOE output
Altera Corporation
February 2007
Figure 2–6