EPF8452AQC160-4 Altera, EPF8452AQC160-4 Datasheet - Page 33
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EPF8452AQC160-4
Manufacturer Part Number
EPF8452AQC160-4
Description
IC FLEX 8000A FPGA 4K 160-PQFP
Manufacturer
Altera
Series
FLEX 8000r
Datasheet
1.EPF8282ATC100-3.pdf
(62 pages)
Specifications of EPF8452AQC160-4
Number Of Logic Elements/cells
336
Number Of Labs/clbs
42
Number Of I /o
120
Number Of Gates
4000
Voltage - Supply
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
160-MQFP, 160-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Total Ram Bits
-
Other names
544-2259
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPF8452AQC160-4
Manufacturer:
GENESIS
Quantity:
569
Part Number:
EPF8452AQC160-4
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
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Table 17. FLEX 8000 Internal Timing Parameters
IOD
IOC
IOE
IOCO
IOCOMB
IOSU
IOH
IOCLR
IN
OD1
OD2
OD3
XZ
ZX1
ZX2
ZX3
Table 18. FLEX 8000 LE Timing Parameters
LUT
CLUT
RLUT
GATE
CASC
CICO
CGEN
CGENR
C
CH
CL
CO
COMB
SU
H
PRE
CLR
Symbol
Symbol
IOE register data delay
IOE register control signal delay
Output enable delay
IOE register clock-to-output delay
IOE combinatorial delay
IOE register setup time before clock; IOE register recovery time after asynchronous clear
IOE register hold time after clock
IOE register clear delay
Input pad and buffer delay
Output buffer and pad delay, slow slew rate = off, V
Output buffer and pad delay, slow slew rate = off, V
Output buffer and pad delay, slow slew rate = on, C1 = 35 pF
Output buffer disable delay, C1 = 5 pF
Output buffer enable delay, slow slew rate = off, V
Output buffer enable delay, slow slew rate = off, V
Output buffer enable delay, slow slew rate = on, C1 = 35 pF
LUT delay for data-in
LUT delay for carry-in
LUT delay for LE register feedback
Cascade gate delay
Cascade chain routing delay
Carry-in to carry-out delay
Data-in to carry-out delay
LE register feedback to carry-out delay
LE register control signal delay
LE register clock high time
LE register clock low time
LE register clock-to-output delay
Combinatorial delay
LE register setup time before clock; LE register recovery time after asynchronous preset, clear, or
load
LE register hold time after clock
LE register preset delay
LE register clear delay
FLEX 8000 Programmable Logic Device Family Data Sheet
Note (1)
Note (1)
Parameter
Parameter
CCIO
CCIO
CCIO
CCIO
= 5.0 V, C1 = 35 pF
= 3.3 V, C1 = 35 pF
= 5.0 V C1 = 35 pF
= 3.3 V C1 = 35 pF
(3)
(3)
(2)
(2)
(2)
(2)
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