EPF10K10TI144-4N Altera, EPF10K10TI144-4N Datasheet - Page 27
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EPF10K10TI144-4N
Manufacturer Part Number
EPF10K10TI144-4N
Description
IC FLEX 10K FPGA 10K 144-TQFP
Manufacturer
Altera
Series
FLEX-10K®r
Datasheet
1.EPF10K10ATC100-3.pdf
(128 pages)
Specifications of EPF10K10TI144-4N
Number Of Logic Elements/cells
576
Number Of Labs/clbs
72
Total Ram Bits
6144
Number Of I /o
102
Number Of Gates
31000
Voltage - Supply
4.5 V ~ 5.5 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2204
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPF10K10TI144-4N
Manufacturer:
Altera
Quantity:
135
Part Number:
EPF10K10TI144-4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
For improved routing, the row interconnect is comprised of a combination
of full-length and half-length channels. The full-length channels connect
to all LABs in a row; the half-length channels connect to the LABs in half
of the row. The EAB can be driven by the half-length channels in the left
half of the row and by the full-length channels. The EAB drives out to the
full-length channels. In addition to providing a predictable, row-wide
interconnect, this architecture provides increased routing resources. Two
neighboring LABs can be connected using a half-row channel, thereby
saving the other half of the channel for the other half of the row.
Table 7
each FLEX 10K device.
In addition to general-purpose I/O pins, FLEX 10K devices have six
dedicated input pins that provide low-skew signal distribution across the
device. These six inputs can be used for global clock, clear, preset, and
peripheral output enable and clock enable control signals. These signals
are available as control signals for all LABs and IOEs in the device.
The dedicated inputs can also be used as general-purpose data inputs
because they can feed the local interconnect of each LAB in the device.
However, the use of dedicated inputs as data inputs can introduce
additional delay into the control signal network.
Table 7. FLEX 10K FastTrack Interconnect Resources
EPF10K10
EPF10K10A
EPF10K20
EPF10K30
EPF10K30A
EPF10K40
EPF10K50
EPF10K50V
EPF10K70
EPF10K100
EPF10K100A
EPF10K130V
EPF10K250A
Device
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
summarizes the FastTrack Interconnect resources available in
Rows
10
12
16
20
3
6
6
8
9
Channels per
Row
144
144
216
216
216
312
312
312
456
Columns
24
24
36
36
36
52
52
52
76
Channels per
Column
24
24
24
24
24
24
24
32
40
27