EP1C12Q240C6N Altera, EP1C12Q240C6N Datasheet - Page 86
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EP1C12Q240C6N
Manufacturer Part Number
EP1C12Q240C6N
Description
IC CYCLONE FPGA 12K LE 240-PQFP
Manufacturer
Altera
Series
Cyclone®r
Datasheet
1.EP1C3T144C8.pdf
(106 pages)
Specifications of EP1C12Q240C6N
Number Of Logic Elements/cells
12060
Number Of Labs/clbs
1206
Total Ram Bits
239616
Number Of I /o
173
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
240-MQFP, 240-PQFP
Family Name
Cyclone®
Number Of Logic Blocks/elements
12060
# I/os (max)
173
Frequency (max)
405.2MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
12060
Ram Bits
239616
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1793
EP1C12Q240C6N
EP1C12Q240C6N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1C12Q240C6N
Manufacturer:
ALTERA
Quantity:
20 000
Company:
Part Number:
EP1C12Q240C6NAA
Manufacturer:
ALTERA
Quantity:
3 000
Cyclone Device Handbook, Volume 1
4–16
Preliminary
t
t
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I N S U
I N H
O U T C O
I N S U P L L
I N H P L L
Table 4–29. Cyclone Global Clock External I/O Timing Parameters
Symbol
Setup time for input or bidirectional pin using IOE input
register with global clock fed by
Hold time for input or bidirectional pin using IOE input
register with global clock fed by
Clock-to-output delay output or bidirectional pin using IOE
output register with global clock fed by
Setup time for input or bidirectional pin using IOE input
register with global clock fed by Enhanced PLL with default
phase setting
Hold time for input or bidirectional pin using IOE input
register with global clock fed by enhanced PLL with default
phase setting
Figure 4–2. External Timing in Cyclone Devices
All external I/O timing parameters shown are for 3.3-V LVTTL I/O
standard with the maximum current strength and fast slew rate. For
external I/O timing using standards other than LVTTL or for different
current strengths, use the I/O standard input and output delay adders in
Tables 4–40
Table 4–29
clock networks.
Dedicated
Clock
Parameter
shows the external I/O timing parameters when using global
through 4–44.
CLK
CLK
pin
pin
CLK
pin
Output Register
Input Register
OE Register
D
D
D
CLRN
CLRN
CLRN
PRN
PRN
PRN
Q
Q
Q
Notes
C
LOAD
(1),
(2)
= 10 pF
(Part 1 of 2)
Conditions
Altera Corporation
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—
—
—
—
XZ
ZX
INSU
INH
OUTCO
Bidirectional
Pin
May 2008