EP2S30F672C5N Altera, EP2S30F672C5N Datasheet - Page 155
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EP2S30F672C5N
Manufacturer Part Number
EP2S30F672C5N
Description
IC STRATIX II FPGA 30K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S30F672C5N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
500
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
33880
# I/os (max)
500
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
Family Type
Stratix II
No. Of I/o's
500
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Operating Temperature Range
0°C To +85°C
Logic Case Style
BGA
No. Of Pins
672
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1898
EP2S30F672C5N
EP2S30F672C5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S30F672C5N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S30F672C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
April 2011
Note to
(1)
25-Ω R
3.3/2.5
50-Ω R
3.3/2.5/1.8
50-Ω R
R
C
C
C
C
C
C
Table 5–31. Series & Differential On-Chip Termination Specification for Left & Right I/O Banks
Table 5–32. Stratix II Device Capacitance
D
I O T B
I O L R
C L K T B
C L K L R
C L K L R +
O U T F B
Symbol
Symbol
Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement
accuracy is within ±0.5pF
S
S
S
Table
1.5
5–32:
Input capacitance on I/O pins in I/O banks 3, 4, 7, and 8.
Input capacitance on I/O pins in I/O banks 1, 2, 5, and 6, including high-
speed differential receiver and transmitter pins.
Input capacitance on top/bottom clock input pins:
CLK[12..15]
Input capacitance on left/right clock inputs:
Input capacitance on left/right clock inputs:
CLK11
Input capacitance on dual-purpose clock output/feedback pins in PLL
banks 9, 10, 11, and 12.
Internal differential termination for
LVDS or HyperTransport technology
(100-Ω setting)
Internal series termination without
calibration (25-Ω setting)
Internal series termination without
calibration (50-Ω setting)
Internal series termination without
calibration (50-Ω setting)
.
Description
Pin Capacitance
Table 5–32
.
shows the Stratix II device family pin capacitance.
Parameter
Note (1)
V
V
V
V
C C I O
C C I O
C C I O
C C I O
CLK0
CLK1
Conditions
= 3.3/2.5 V
= 3.3/2.5/1.8 V
= 1.5 V
= 2.5 V
,
,
CLK[4..7]
CLK2
CLK3
,
,
CLK8
CLK9
Stratix II Device Handbook, Volume 1
and
,
, and
DC & Switching Characteristics
Commercial
CLK10
Max
±30
±30
±36
±20
Resistance Tolerance
.
Industrial
Typical
5.0
6.1
6.0
6.1
3.3
6.7
Max
±30
±30
±36
±25
Unit
Unit
%
%
%
%
pF
pF
pF
pF
pF
pF
5–19