EP2S30F672C5N Altera, EP2S30F672C5N Datasheet - Page 184
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EP2S30F672C5N
Manufacturer Part Number
EP2S30F672C5N
Description
IC STRATIX II FPGA 30K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S30F672C5N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
500
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
33880
# I/os (max)
500
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
Family Type
Stratix II
No. Of I/o's
500
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Operating Temperature Range
0°C To +85°C
Logic Case Style
BGA
No. Of Pins
672
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1898
EP2S30F672C5N
EP2S30F672C5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S30F672C5N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S30F672C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Timing Model
5–48
Stratix II Device Handbook, Volume 1
t
t
t
t
t
t
t
t
t
t
t
t
C I N
C O U T
P L L C I N
P L L C O U T
C I N
C O U T
P L L C I N
P L L C O U T
C I N
C O U T
P L L C I N
P L L C O U T
Table 5–62. EP2S130 Row Pins Regional Clock Timing Parameters
Table 5–63. EP2S130 Row Pins Global Clock Timing Parameters
Table 5–64. EP2S180 Column Pins Regional Clock Timing Parameters
Parameter
Parameter
Parameter
Industrial
Industrial
Industrial
-0.113
-0.108
-0.087
-0.082
-0.307
-0.464
1.680
1.685
1.690
1.695
2.001
1.844
Minimum Timing
Minimum Timing
Minimum Timing
EP2S180 Clock Timing Parameters
Tables 5–64
for EP2S180 devices.
Commercial
Commercial
Commercial
-0.124
-0.119
-0.097
-0.092
-0.297
-0.462
1.760
1.765
1.770
1.775
2.095
1.930
through
5–67
-3 Speed
-3 Speed
-3 Speed
Grade
-0.124
Grade
-0.075
-0.079
Grade
-0.201
3.070
3.066
3.075
3.071
show the maximum clock timing parameters
3.643
3.389
0.053
-0.12
-4 Speed
-4 Speed
-4 Speed
Grade
-0.138
-0.142
Grade
-0.089
-0.093
Grade
-0.232
3.351
3.347
3.362
3.358
3.984
3.706
0.046
-5 Speed
-5 Speed
-5 Speed
Altera Corporation
Grade
-0.168
-0.173
Grade
-0.115
Grade
-0.276
3.892
3.887
3.905
3.900
4.634
4.310
0.048
-0.11
April 2011
Unit
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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ns