EP2S30F672C5N Altera, EP2S30F672C5N Datasheet - Page 235
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EP2S30F672C5N
Manufacturer Part Number
EP2S30F672C5N
Description
IC STRATIX II FPGA 30K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S30F672C5N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
500
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
33880
# I/os (max)
500
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
Family Type
Stratix II
No. Of I/o's
500
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Operating Temperature Range
0°C To +85°C
Logic Case Style
BGA
No. Of Pins
672
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1898
EP2S30F672C5N
EP2S30F672C5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S30F672C5N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S30F672C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
April 2011
January 2005,
v2.0
October 2004,
v1.2
July 2004, v1.1
February 2004,
v1.0
Table 5–103. Document Revision History (Part 3 of 3)
Document
Date and
Version
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
Added document to the Stratix II Device Handbook.
Updated the “Power Consumption” section.
Added the “High-Speed I/O Specifications” and
“On-Chip Termination Specifications” sections.
Removed the ESD Protection Specifications
section.
Updated Tables 5–3 through 5–13, 5–16 through
5–18, 5–21, 5–35, 5–39, and 5–40.
Updated tables in “Timing Model” section.
Added Tables 5–30 and 5–31.
Updated Table 5–3.
Updated introduction text in the “PLL Timing
Specifications” section.
Re-organized chapter.
Added typical values and C
Added undershoot specification to Note (4) for
Tables 5–1 through 5–9.
Added Note (1) to Tables 5–5 and 5–6.
Added V
Added “I/O Timing Measurement Methodology”
section.
Added Table 5–72.
Updated Tables 5–1 through 5–2 and Tables 5–24
through 5–29.
I D
and V
Changes Made
I C M
to Table 5–10.
O U T F B
to Table 5–32.
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Summary of Changes
—
—
—
—
5–99