EP3C16F484C8N Altera, EP3C16F484C8N Datasheet - Page 189
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C8N
Manufacturer Part Number
EP3C16F484C8N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C8N.pdf
(274 pages)
Specifications of EP3C16F484C8N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2474
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA
Quantity:
331
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA44
Quantity:
120
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
Figure 9–10. Word-Wide Multi-Device AP Configuration
Notes to
(1) Connect the pull-up resistors to the V
(2) Connect the pull-up resistor to the V
(3) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(4) The MSEL pin settings vary for different configuration voltage standards and POR time. You must set the master device in AP mode and the slave
(5) The AP configuration ignores the WAIT signal during configuration mode. However, if you are accessing flash during user mode with user logic,
(6) Connect the repeater buffers between the Cyclone III master device and slave devices for DATA[15..0] and DCLK. All I/O inputs must maintain
© December 2009
devices in FPP mode. To connect MSEL[3..0] for the master device in AP mode and the slave devices in FPP mode, refer to
page
you can optionally use the normal I/O pin to monitor the WAIT signal from the Numonyx P30 or P33 flash.
a maximum AC voltage of 4.1 V. The output resistance of the repeater buffers must fit the maximum overshoot equation outlined in
and JTAG Pin I/O Requirements” on page
Figure
9–11. Connect the MSEL pins directly to V
9–10:
1
Altera Corporation
Numonyx P30/P33 Flash
Word-Wide Multi-Device AP Configuration
The more efficient setup is one in which some of the slave devices are connected to the
LSB of DATA[7..0]and the remaining slave devices are connected to the MSB of
DATA[15..8]. In the word-wide multi-device AP configuration, the nCEO pin of the
master device enables two separate daisy-chains of slave devices, allowing both
chains to be programmed concurrently, as shown in
In a multi-device AP configuration, the board trace length between the parallel flash
and the master device must follow the recommendations listed in
DQ[15:0]
A[24:1]
RST#
ADV#
WAIT
WE#
OE#
CLK
CE#
CCIO
CCIO
supply voltage of the I/O bank in which the nCE pin resides.
supply of the bank in which the pin resides.
9–7.
GND
10 k
V CCIO (1)
Buffers (6)
nCE
DCLK
nRESET
FLASH_nCE
nOE
nAVD
nWE
I/O (5)
DATA[15..0]
PADD[23..0]
Cyclone III Master Device
CCA
10 k
or GND.
V CCIO (1)
MSEL[3..0]
10 k
V CCIO (1)
nCEO
DQ[15..8]
10 k
V CCIO (2)
DQ[7..0]
(4)
nCE
DATA[7..0]
DCLK
nCE
DATA[7..0]
DCLK
Cyclone III Slave Device
Cyclone III Slave Device
MSEL[3..0]
MSEL[3..0]
nCEO
10 k
nCEO
V CCIO (1)
10 k
V CCIO (2)
DQ[15..8]
DQ[7..0]
(4)
(4)
nCE
DATA[7..0]
DCLK
nCE
DATA[7..0]
DCLK
Cyclone III Slave Device
Cyclone III Slave Device
Figure
Cyclone III Device Handbook, Volume 1
MSEL[3..0]
MSEL[3..0]
9–10.
nCEO
nCEO
(4)
N.C. (3)
(4)
N.C. (3)
Table
9–12.
Table 9–7 on
“Configuration
9–29