EP3C16F484C8N Altera, EP3C16F484C8N Datasheet - Page 237
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C8N
Manufacturer Part Number
EP3C16F484C8N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C8N.pdf
(274 pages)
Specifications of EP3C16F484C8N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2474
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA
Quantity:
331
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA44
Quantity:
120
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Remote System Upgrade
Remote System Upgrade
Functional Description
© December 2009
1
Altera Corporation
Cyclone III devices support remote system upgrade in AS and AP configuration
schemes. Cyclone III LS devices support remote system upgrade in the AS
configuration scheme only. Remote system upgrade can also be implemented with
advanced Cyclone III features such as real-time decompression of configuration data
in the AS configuration scheme.
■
■
■
The dedicated remote system upgrade circuitry in Cyclone III device family manages
remote configuration and provides error detection, recovery, and status information.
User logic or a Nios
array provides access to the remote configuration data source and an interface to the
configuration memory.
Configuration memory refers to serial configuration devices (EPCS) or supported
parallel flash memory, and depends on the configuration scheme that you use.
The remote system upgrade process of Cyclone III device family involves the
following steps:
1. A Nios II processor (or user logic) implemented in the Cyclone III device family
2. The Nios II processor (or user logic) writes this new configuration data into a
3. The Nios II processor (or user logic) starts a reconfiguration cycle with the new or
4. The dedicated remote system upgrade circuitry detects and recovers from any
The serial configuration device uses the AS configuration scheme to configure
Cyclone III or Cyclone III LS devices
The supported parallel flash uses the AP configuration scheme to configure
Cyclone III devices
Remote system upgrade is not supported in the multi-device configuration chain
for any configuration scheme.
logic array receives new configuration data from a remote location. The connection
to the remote source is a communication protocol such as the transmission control
protocol/Internet protocol (TCP/IP), peripheral component interconnect (PCI),
user datagram protocol (UDP), universal asynchronous receiver/transmitter
(UART), or a proprietary interface.
configuration memory.
updated configuration data.
error that might occur during or after the reconfiguration cycle, and provides error
status information to the user design.
®
II processor implemented in the Cyclone III device family logic
Cyclone III Device Handbook, Volume 1
9–77