EP3C16F484C8N Altera, EP3C16F484C8N Datasheet - Page 340
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C8N
Manufacturer Part Number
EP3C16F484C8N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C8N.pdf
(274 pages)
Specifications of EP3C16F484C8N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2474
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA
Quantity:
331
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA44
Quantity:
120
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
2–22
Table 2–32. FPGA Sampling Window (SW) Requirement—Read Side
Cyclone III Device Handbook, Volume 2
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
Note to
(1) Column I/Os refer to top and bottom I/Os. Row I/Os refer to right and left I/Os. Wraparound mode refers to the combination of column and row
I/Os.
Memory Standard
Table
2–32:
f
Table 2–31. Cyclone III LS Devices LVDS Receiver Timing Specifications
External Memory Interface Specifications
Cyclone III LS devices support external memory interfaces up to 200 MHz. The
external memory interfaces for Cyclone III LS devices are auto-calibrating and easy to
implement.
Table 2–32
Cyclone III LS devices and are useful when performing memory interface timing
analysis.
For more information about external memory system specifications, refer to the
External Memory Interface
(Part 2 of 2) (Preliminary)
Input jitter
tolerance
t
Notes to
(1) True LVDS receiver is supported at all banks.
(2) t
LOCK
(2)
LOC K
Symbol
Table
is the time required for the PLL to lock from the end of device configuration.
and
Setup
1050
705
675
900
785
800
765
745
945
2–31:
Column I/Os (ps)
Table 2–33
Modes
—
—
Hold
650
620
845
720
740
990
710
690
890
Handbook.
list the external memory interface specifications for
C7
C8
I7
Min
—
—
Setup
1065
C7 and I7
770
795
910
930
915
855
880
955
(Note 1)
Row I/Os (ps)
Max
500
1
(Preliminary)
Hold
1005
715
740
855
870
855
800
825
900
Chapter 2: Cyclone III LS Device Data Sheet
© December 2009 Altera Corporation
Min
—
—
Wraparound Mode (ps)
(Note 1)
Setup
1085
1210
1130
1115
1185
1040
1000
C8
985
970
Switching Characteristics
Max
550
1
1030
1075
1055
1125
1150
Hold
930
915
985
945
Unit
ps
ps