EP3C16F484C8N Altera, EP3C16F484C8N Datasheet - Page 43
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C8N
Manufacturer Part Number
EP3C16F484C8N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C8N.pdf
(274 pages)
Specifications of EP3C16F484C8N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2474
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA
Quantity:
331
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA44
Quantity:
120
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 3: Memory Blocks in the Cyclone III Device Family
Overview
Mixed-Width Support
Asynchronous Clear
© December 2009
1
Altera Corporation
Figure 3–5. Cyclone III Device Family Address Clock Enable During Write Cycle Waveform
M9K memory blocks support mixed data widths. When using simple dual-port, true
dual-port, or FIFO modes, mixed width support allows you to read and write
different data widths to an M9K memory block. For more information about the
different widths supported per memory mode, refer to
page
The Cyclone III device family supports asynchronous clears for read address
registers, output registers, and output latches only. Input registers other than read
address registers are not supported. When applied to output registers, the
asynchronous clear signal clears the output registers and the effects are immediately
seen. If your RAM does not use output registers, you can still clear the RAM outputs
using the output latch asynchronous clear feature.
Asserting asynchronous clear to the read address register during a read operation
might corrupt the memory content.
Figure 3–6
Figure 3–6. Output Latch Asynchronous Clear Waveform
aclr at latch
latched address
(inside memory)
3–8.
contents at a0
contents at a1
contents at a2
contents at a3
contents at a4
contents at a5
addressstall
wraddress
aclr
clk
q
shows the functional waveform for the asynchronous clear feature.
inclock
wren
data
an
XX
a0
00
a1
XX
a0
01
a1
a2
XX
01
02
a2
XX
XX
XX
a1
02
a3
03
00
“Memory Modes” on
Cyclone III Device Handbook, Volume 1
04
a4
a0
a4
03
a5
05
a1
04
a5
05
a6
06
3–7