EP3C16F484C8N Altera, EP3C16F484C8N Datasheet - Page 157
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C8N
Manufacturer Part Number
EP3C16F484C8N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C8N.pdf
(274 pages)
Specifications of EP3C16F484C8N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2474
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA
Quantity:
331
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA44
Quantity:
120
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 8: External Memory Interfaces in the Cyclone III Device Family
Cyclone III Device Family Memory Interfaces Features
Figure 8–6. Extending the OE Disable by Half a Clock Cycle for a Write Transaction
Note to
(1) The waveform reflects the software simulation result. The OE signal is an active low on the device. However, the Quartus II software implements
OCT
PLL
© January 2010 Altera Corporation
the signal as an active high and automatically adds an inverter before the A
Figure
8–6:
f
f
1
from System Clock)
(outclock for DQS)
-90 phase shifted
(from logic array)
(from logic array)
(from logic array)
(from logic array)
(outclock for DQ,
Figure 8–6
high-impedance state by half a clock cycle during a write operation.
o
Cyclone III device family supports calibrated on-chip series termination (R
both vertical and horizontal I/O banks. To use the calibrated OCT, you must use the
RUP and RDN pins for each R
each OCT calibration block to calibrate one type of termination with the same V
that given side.
For more information about Cyclone III device family OCT calibration block, refer to
the
When interfacing with external memory, the PLL is used to generate the memory
system clock, the write clock, the capture clock and the logic-core clock. The system
clock generates the DQS write signals, commands, and addresses. The write-clock is
shifted by -90° from the system clock and generates the DQ signals during writes. You
can use the PLL reconfiguration feature to calibrate the read-capture phase shift to
balance the setup and hold margins.
The PLL is instantiated in the ALTMEMPHY megafunction. All outputs of the PLL are
used when the ALTMEMPHY megafunction is instantiated to interface with external
memories.
For more information about the usage of PLL outputs by the ALTMEMPHY
megafunction, refer to
System clock
OE for DQS
Write Clock
OE for DQ
datain_h
datain_I
Cyclone III Device I/O Features
DQS
DQ
shows how the second output enable register extends the DQS
90
o
Literature: External Memory
a Clock
by Half
Delay
Cycle
S
OCT control block (one for each side). You can use
chapter.
Preamble
OE
register D input.
D1
D0
D0
D1
Interfaces.
D3
D2
D2
(Note 1)
Cyclone III Device Handbook, Volume 1
D3
Postamble
S
OCT) in
CCIO
8–13
for