EP3C16F484C8N Altera, EP3C16F484C8N Datasheet - Page 264
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C8N
Manufacturer Part Number
EP3C16F484C8N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C8N.pdf
(274 pages)
Specifications of EP3C16F484C8N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2474
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA
Quantity:
331
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA44
Quantity:
120
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
11–10
Table 11–8. CRC Block Input and Output Ports (Part 2 of 2)
Recovering from CRC Errors
Cyclone III Device Handbook, Volume 1
.ldsrc (<ldsrc
source>)
.crcerror
(<crcerror
indicator
output>)
.regout
(<registered
output>)
.cyclecomplete
(<cyclone
complete
indicator
output>)
Port
The system that the Altera FPGA resides in must control device reconfiguration. After
detecting an error on the CRC_ERROR pin, strobing the nCONFIG low directs the
system to perform the reconfiguration at a time when it is safe for the system to
reconfigure the FPGA.
When the data bit is rewritten with the correct value by reconfiguring the device, the
device functions correctly.
While soft errors are uncommon in Altera devices, certain high-reliability applications
might require a design to account for these errors.
Input/Output
Output
Output
Output
Input
This signal is an input into the error detection block. If ldsrc=0, the
pre-computed CRC register is selected for loading into the 32-bit shift register
at the rising edge of clk when shiftnld=0. If ldsrc=1, the signature
register (result of the CRC calculation) is selected for loading into the shift
register at the rising edge of clk when shiftnld=0. This port is ignored
when shiftnld=1. This port is required.
This signal is the output of the cell that is synchronized to the internal
oscillator of the device (80-MHz internal oscillator) and not to the clk port. It
asserts high if the error block detects that a SRAM bit has flipped and the
internal CRC computation has shown a difference with respect to the pre-
computed value. This signal must be connected either to an output pin or a
bidirectional pin. If it is connected to an output pin, you can only monitor the
CRC_ERROR pin (the core cannot access this output). If the CRC_ERROR
signal is used by core logic to read error detection logic, this signal must be
connected to a BIDIR pin. The signal is fed to the core indirectly by feeding a
BIDIR pin that has its output enable port connected to VCC
page
This signal is the output of the error detection shift register synchronized to
the clk port, to be read by core logic. It shifts one bit at each cycle, so you
should clock the clk signal 31 cycles to read out the 32 bits of the shift
register.
This signal is for cycloneiiils_crcblock only. This output signal is
synchronized to the internal oscillator of the device (80-MHz internal
oscillator), and not to the clk port. The signal asserts high for one clock
cyclone every time an error detection cyclone completes.
11–8).
Chapter 11: SEU Mitigation in the Cyclone III Device Family
Definition
© December 2009 Altera Corporation
Recovering from CRC Errors
(Figure 11–3 on